Yield challenges in wafer stacking technology

Kim, Min Jung; Sung, Jaeyong

doi:10.1016/j.microrel.2008.03.010

Cited by 12 publications

(4 citation statements)

References 5 publications

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“…For the test cost, we assume a test cost per die t die = 0.23 cent [3,11]. We assume that the interconnect test are 100 less in cost, similar as in [27].…”

Section: Process Parametersmentioning

confidence: 99%

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Taouil

Hamdioui

2012

J Electron Test

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Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the tradeoff between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85 %, a relative yield improvement of 118.79 % is obtained with two redundant layers, while this is 14.03 % only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68 % when using layer redundancy and only with 12.48 % when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions.

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“…For the test cost, we assume a test cost per die t die = 0.23 cent [3,11]. We assume that the interconnect test are 100 less in cost, similar as in [27].…”

Section: Process Parametersmentioning

confidence: 99%

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Taouil

Hamdioui

2012

J Electron Test

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“…It should be noted that wafer stacking is a serial process and, as a consequence, the extent of three-dimensionality that could be achieved is limited; hence, wafer stacking actually achieves a 2.5D architecture, and not a truly 3D architecture. In addition, wafer stacking comes with its own challenge: the alignment of the vias [ 14 , 15 ].…”

Section: Introductionmentioning

confidence: 99%

Assembly of a 3D Cellular Computer Using Folded E-Blocks

et al. 2016

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The assembly of integrated circuits in three dimensions (3D) provides a possible solution to address the ever-increasing demands of modern day electronic devices. It has been suggested that by using the third dimension, devices with high density, defect tolerance, short interconnects and small overall form factors could be created. However, apart from pseudo 3D architecture, such as monolithic integration, die, or wafer stacking, the creation of paradigms to integrate electronic low-complexity cellular building blocks in architecture that has tile space in all three dimensions has remained elusive. Here, we present software and hardware foundations for a truly 3D cellular computational devices that could be realized in practice. The computing architecture relies on the scalable, self-configurable and defect-tolerant cell matrix. The hardware is based on a scalable and manufacturable approach for 3D assembly using folded polyhedral electronic blocks (E-blocks). We created monomers, dimers and 2 × 2 × 2 assemblies of polyhedral E-blocks and verified the computational capabilities by implementing simple logic functions. We further show that 63.2% more compact 3D circuits can be obtained with our design automation tools compared to a 2D architecture. Our results provide a proof-of-concept for a scalable and manufacture-ready process for constructing massive-scale 3D computational devices.

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“…[8] ). Such vertical integration solutions suffer from power dissipation problems, low interconnect density (because of a poor accuracy of wafer alignment, as compared with that of photolithographic masks defining features on a single wafer for multiple metallization layers), low yields (due to the lack of the known-good-die assembly), and poor cost efficiency [9] . As a result, such solutions cannot provide adequate density and throughput that will be required, for example, for real time signal processing from focal plane arrays [10] .…”

Section: Introductionmentioning

confidence: 99%

3D CMOS-memristor hybrid circuits

Cheng

Strukov

2012

Proceedings of the 2012 ACM International Symposium on International Symposium on Physical Design

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In this paper, we give an overview of our recent research efforts on monolithic 3D integration of CMOS and memristive nanodevices. These hybrid circuits combine a CMOS subsystem with several layers of nanowire crossbars, consisting of arrays of two-terminal memristors, all connected by an area-distributed interface between the CMOS subsystem and the crossbars. This approach combines the advantages of CMOS technology, including its high flexibility, functionality and yield, with the extremely high density of nanowires, nanodevices and interface vias. As a result, the 3D hybrids can overcome limitations pertinent to other 3D integration techniques (such as through-silicon vias) and enable 3D circuits with unprecedented memory density (up to 10 14 bits on a single 1cm 2 chip) and aggregate interlayer communication bandwidth (up to 10 18 bits per second per cm 2 ) at manageable power dissipation. Such performance represents a significant step towards addressing the most pressing needs of modern compact electronic systems.

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Yield challenges in wafer stacking technology

Cited by 12 publications

References 5 publications

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Assembly of a 3D Cellular Computer Using Folded E-Blocks

3D CMOS-memristor hybrid circuits

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