An RDL-configurable 3D memory tier to replace on-chip SRAM

Facchini,; Marchal,; Catthoor,; Dehaene,

doi:10.1109/date.2010.5457194

Cited by 6 publications

(2 citation statements)

References 8 publications

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“…The RLC values of the micro-bumps are listed in Table IV. In addition, the low latency RDL is modeled using a lumped RC model using the values obtained from [11].…”

Section: A Bonding Wire Modelmentioning

confidence: 99%

A case for 3D stacked analog circuits in high-speed sensing systems

Abdel-Majeed

Chen

Annavaram

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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In order to build high performance real-time sensing systems every building block in the system should be built with a technology that allows that building block to achieve its best performance. Technologies like BJT and BICMOS are better suited for building basic analog blocks like input buffers and power amplifiers, while CMOS is the best choice for digital data processing. To build mixed-technology systems traditionally system-in-package (SiP) techniques are used. SiP integration uses bonding wires or flip chip instead of on-chip integration. In this paper we study the feasibility of using 3D stacking to integrate heterogeneous blocks built using different technologies within a real-time sensing system. Several of the previous studies on 3D stacking focused on integrating multiple digital blocks and using through-silicon-vias (TSVs) to transfer digital signals between the layers in a stack. In this paper we study the behavior of the analog signals traversing through TSVs and measure how well 3D stacking can enhance or limit the performance of analog and digital stacking. In order to quantify the power and performance characteristics, we modeled bonding wire, flip chip, and through-silicon-via (TSV) interfaces. Using these models we show that 3D stacking of analog and analog/digital components can double the bandwidth, increase sampling frequency by nearly two orders magnitude and and improve the signal integrity by 3 dB compared to bond wires.

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“…The RLC values of the micro-bumps are listed in Table IV. In addition, the low latency RDL is modeled using a lumped RC model using the values obtained from [11].…”

Section: A Bonding Wire Modelmentioning

confidence: 99%

A case for 3D stacked analog circuits in high-speed sensing systems

Abdel-Majeed

Chen

Annavaram

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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show abstract

“…Instead of using a crossbar switch, AND logic is used in order to reduce the latency. In [46], customizable redistribution layer (RDL) routing was proposed. The RDL, which is a plated metal layer with superior electrical characteristics than typical metal wire, enables connecting each core and memory cell without any switch connection.…”

Section: Related Workmentioning

confidence: 99%

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

Kang

Benini

Micheli

2015

IEEE Trans. VLSI Syst.

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Abstract-3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and low yield). In this paper, we propose a new TSV sharing method for a circuit-switched 3-D mesh-of-tree (MoT) interconnect, which supports high-throughput and lowlatency communication between processing cores and 3-D stacked multibanked L2 scratchpad memory. The proposed method supports traffic balancing and TSV-failure tolerant routing. The proposed method advocates a modular design strategy to allow stacking multiple identical memory dies without the need for different masks for dies at different levels in the memory stack. We also investigate various parameters of 3-D memory stacking (e.g., fabrication technology, TSV bonding technique, number of memory tiers, and TSV sharing scheme) that affect interconnect latency, system performance, and fabrication cost. Compared to conventional MoT interconnect [6] that is straightforwardly adapted to 3-D integration, the proposed method yields up to ×2.11 and ×1.11 improvements in terms of cost efficiency (i.e., performance/cost) for microbump TSV bonding and direct Cu-Cu TSV bonding techniques, respectively. Index Terms-3-D integration, multicore, networks-on-chip (NoC), scratchpad memory (SPM).

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A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh

Vignon

Cosemans

Maex³

et al. 2012

Solid-State Electronics

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This paper presents a low-leakage 128 kbit dynamic memory based on a 2T dynamic cell. The design is implemented in a logic 90 nm technology and achieves a low static power consumption of 130 µW and an access time of 2 ns. It has a worst case retention time of 175 µs. This performance is achieved by introducing an optimized hierarchical organization and peripheral circuits for the read, the write and the refresh operations. A novel writing mechanism for 2T cells using a double phase approach is demonstrated. The area penalty of using short read bitlines is alleviated using a charge transfer sense amplifier (SA). A novel local write sense amplifier (WSA) that can operate as a latch makes it possible to perform the refresh operation at the local level, improving the energy efficiency of the refresh operation.The memory includes an integrated automatic refresh mechanism. Most read and write operations can still be performed during refresh cycles. In cases where the accessed address conflicts with the refresh operation, the memory handles access recovery internally.

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An RDL-configurable 3D memory tier to replace on-chip SRAM

Cited by 6 publications

References 8 publications

A case for 3D stacked analog circuits in high-speed sensing systems

A case for 3D stacked analog circuits in high-speed sensing systems

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh

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