A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh

Abstract

This paper presents a low-leakage 128 kbit dynamic memory based on a 2T dynamic cell. The design is implemented in a logic 90 nm technology and achieves a low static power consumption of 130 µW and an access time of 2 ns. It has a worst case retention time of 175 µs. This performance is achieved by introducing an optimized hierarchical organization and peripheral circuits for the read, the write and the refresh operations. A novel writing mechanism for 2T cells using a double phase approach is demonstrated. The area penalty of using short read bitlines is alleviated using a charge transfer sense amplifier (SA). A novel local write sense amplifier (WSA) that can operate as a latch makes it possible to perform the refresh operation at the local level, improving the energy efficiency of the refresh operation.The memory includes an integrated automatic refresh mechanism. Most read and write operations can still be performed during refresh cycles. In cases where the accessed address conflicts with the refresh operation, the memory handles access recovery internally.

P‐channel logic 2 T eDRAM macro with high retention bit architecture

“…The 2 T structure in mixed type of an n‐channel MOSFET and a p‐channel MOSFET also carries considerable bit‐area penalty due to the large well‐to‐well space. For the competitive bit‐area, the 2 T cell in the same type of MOSFETs could be the most effective option. Moreover, to obtain high data retention, PMOS‐only cells would be preferable because PMOS transistors have significantly lower leakage currents over their NMOS counterparts.…”