Fabrication and Challenges of Cu-to-Cu Wafer Bonding

Kang, Sung-Geun; Lee, Jieun; Kim, Eun‐Sol; Lim, Na-Eun; Kim, Soo-Hyung; Kim, Sung‐Dong; Kim, Sarah Eun-Kyung

doi:10.6117/kmeps.2012.19.2.029

Cited by 19 publications

(6 citation statements)

References 10 publications

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“…This means that the increase in pattern density might not be able to promote stable metallic contact across the dielectric erosion induced by the CMP process. 25) The previous study 26) also reported that Cu bump after the Cu CMP process was locally bonded at the edge of each bump, producing a very weak bond interface. Therefore, the minimization of both Cu pattern dishing and erosion during CMP process seems to be critical for improving Cu-Cu interconnect direct bonding quality and reliability.…”

Section: Resultsmentioning

confidence: 96%

Effects of wet treatment conditions and pattern densities on interfacial bonding characteristics of Cu–Cu direct bonds

Park¹,

Kim²,

Park³

2014

Jpn. J. Appl. Phys.

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Effects of both wet chemical treatments and line pattern densities on the interfacial bonding characteristics of Cu–Cu pattern direct bonds were systematically investigated. The silicon oxide (SiO2) on a parallel Cu lines patterned wafer could be removed effectively by using a solution of buffered oxide etch and sulfuric acid (BOE/H2SO4) to improve the bonding quality of Cu–Cu pattern direct bonds. The Cu surface after BOE/H2SO4 wet pretreatment revealed the complete removal of both the residue particles and the surface oxide layer. After BOE/H2SO4 wet pretreatment, the interfacial adhesion energies of 0.06, 0.09, and 0.23 pattern densities were 7.9, 4.8, and 4.1 J/m2, respectively, where the dielectric erosion due to chemical–mechanical polishing (CMP) process with increasing pattern density significantly affected the Cu–Cu pattern direct bonding quality. Therefore, CMP planarization performance is critical for reliable Cu pattern direct bonding.

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Section: Resultsmentioning

confidence: 96%

Effects of wet treatment conditions and pattern densities on interfacial bonding characteristics of Cu–Cu direct bonds

Park¹,

Kim²,

Park³

2014

Jpn. J. Appl. Phys.

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“…Then, a silicon dioxide (SiO 2 ) dielectric layer 0.3 µm in thickness was formed by dry thermal oxidation at a temperature of 1100 • C. Next, a 1.6 µm-thick layer of silicon nitride (Si 3 N 4 ) was deposited by LPCVD (low pressure chemical vapor deposition) at a temperature of 830 • C. The top electrode was formed by the deposition of in situ n+-doped polysilicon (poly-Si) using LPCVD with a 0.5 µm thickness at 600 • C. The simplified schematic of the manufacturing process is illustrated in Figure 1. It is worth noting that these layers are deposited at varying temperatures, leading to misfit strain at room temperature due to their different CTE, as referenced in [18][19][20][21].…”

Section: Manufacturing Process and Parametrized Samplesmentioning

confidence: 99%

Multi-Step Mechanical and Thermal Homogenization for the Warpage Estimation of Silicon Wafers

Xiang,

Chen,

Deng

et al. 2024

Micromachines

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In response to the increasing demand for high-performance capacitors, with a simultaneous emphasis on minimizing their physical size, a common practice involves etching deep vias and coating them with functional layers to enhance operational efficiency. However, these deep vias often cause warpages during the processing stage. This study focuses on the numerical modeling of wafer warpage that occurs during the deposition of three thin layers onto these vias. A multi-step mechanical and thermal homogenization approach is proposed to estimate the warpage of the silicon wafer. The efficiency and accuracy of this numerical homogenization strategy are validated by comparing detailed and homogenized models. The multi-step homogenization method yields more accurate results compared to the conventional direct homogenization method. Theoretical analysis is also conducted to predict the shape of the wafer warpage, and this study further explores the impact of via depth and substrate thickness.

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“…However, the mismatch in the coefficient of thermal expansion (CTE) of different applied materials induces the wafer warpage during the fabrication processes. [3][4][5][6][7][8] Large wafer warpage is becoming a critical problem causing many issues such as wafer handling, lithography alignment, device reliability, etc. 9,10) The ultrathin wafers are reported to deform easily due to the increase of the elasticity/reduction of stiffness.…”

Section: Introductionmentioning

confidence: 99%

Study of wafer warpage reduction by dicing street

Feng

Shimamoto

Kawagoe³

et al. 2022

Jpn. J. Appl. Phys.

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Wafer warpage occurs during the fabrication process, which induces many issues such as wafer handling, lithography alignment, device reliability. The efficiency of dicing street on wafer warpage reduction is investigated by varying the width, depth, and pitch of dicing. With the finite element method simulation results, decreasing the dicing pitch to a quarter-pitch shows a 43.7% warpage reduction. We reveal that the method of decreasing the dicing pitch is more efficient on wafer warpage reduction than that of increasing the dicing width or depth. Furthermore, the efficiency of warpage reduction by decreasing the dicing pitch is confirmed by experiments, which shows a good agreement with the simulated results. The method of decreasing the dicing pitch cut each part smaller. These small parts deform locally instead of continually over the whole wafer, resulting in an efficient wafer warpage reduction. This research provides guidelines for chiplet design or optimization of chip size to reduce the wafer warpage.

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Fabrication and Challenges of Cu-to-Cu Wafer Bonding

Cited by 19 publications

References 10 publications

Effects of wet treatment conditions and pattern densities on interfacial bonding characteristics of Cu–Cu direct bonds

Effects of wet treatment conditions and pattern densities on interfacial bonding characteristics of Cu–Cu direct bonds

Multi-Step Mechanical and Thermal Homogenization for the Warpage Estimation of Silicon Wafers

Study of wafer warpage reduction by dicing street

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