Constant Impedance Scaling Paradigm for Scaling LC transmission lines

Balachandran, Jayaprakash; Brebels, S.; Carchon, G.; Raedt, W. De; Beyne, Eric; Kuijk, Maarten; Nauwelaers, Bart

doi:10.1109/isqed.2006.38

Cited by 3 publications

(2 citation statements)

References 14 publications

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“…This coupling has two fold impacts -induce crosstalk and lowers the impedance from that of the isolated line. Consequently, there can be two possible strategies for determining s. In [9], the s is adjusted in multiples of interconnect width w such that the crosstalk noise is within an acceptable threshold. In this work, the s is adjusted such that the impedance remains unaltered by the presence of adjacent conductors.…”

Section: Interconnect Designmentioning

confidence: 99%

“…Reverse scaling of the LC transmission lines are analyzed in [9]. Here, we illustrate the methodology for interconnects with different performance requirements as line with minimum delay (LC transmission lines), optimum line for repeater less data transfer, minimum delay-maximum wiring density and minimum delay-minimum power -maximum wiring density.…”

Section: Introductionmentioning

confidence: 99%

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Constant impedance scaling paradigm for interconnect synthesis

Balachandran¹,

Brebels²,

Carchon³

et al. 2006

Proceedings of the 2006 International Workshop on System-Level Interconnect Prediction

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On-chip global interconnects perceived as performance limiters for continued scaling of integrated circuits in nano-CMOS regimes highlight the importance of their proper design and optimization. A constant impedance scaling paradigm is proposed for systematic synthesis of complete interconnects physical parameters from system level performance metrics such as delay, power and wiring density. The methodology is illustrated for different system level targets and optimal physical parameters are deduced.

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Section: Interconnect Designmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%