Extending on-die wiring hierarchy with wafer level packaging concepts

Balachandran, Jayaprakash; Brebels, S.; Carchon, G.; Webers, Tomas; Raedt, W. De; Nauwelaers, Bart; Beyne, Eric

doi:10.1109/iitc.2004.1345705

Cited by 6 publications

(3 citation statements)

References 10 publications

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“…We realized two types of transmission line configurations in the WLP layers namely -Microstrip and Integrated Mesh Power Ground Systems (IMPS) [14]. The IMPS structures simultaneously achieve a high quality signal transmission and Power distribution.…”

Section: Fig 5 Fabricated Wlp Test Chip Cross Sectionmentioning

confidence: 99%

“…Specifically, interconnects at the Wafer Level Packaging layers are well suited for the global wiring applications [14].…”

Section: Fig 3 Propagation Mode Cutoff Frequencies For Different Tecmentioning

confidence: 99%

“…Compared to conventional methods [12,13] using external MCM type and PWB interconnects for on-chip global wiring where flip chip bumps and solder balls are used, the WLP solution uses vias to die pads for interconnection. Thus WLP layers can be viewed as an extension of on-chip global wiring layers than off-chip interconnects [14]. The performances of On-chip global interconnection through conventional packages are limited by parasitics of ESD protection circuits [15] and solder bumps.…”

Section: Introductionmentioning

confidence: 99%

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Package level interconnect options

Balachandran¹,

Brebels²,

Carchon³

et al. 2005

Proceedings of the 2005 International Workshop on System Level Interconnect Prediction

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Scaling enhances intrinsic transistor performance and degrades interconnects. As the technology steps into nanometer era, global interconnects are becoming bottleneck for overall chip performance. In this paper, we show package level interconnects are an effective alternative for on-chip global wiring. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performancebandwidth, bandwidth density, latency and power consumptionof the package level transmission lines with conventional on-chip global interconnects for different ITRS technology nodes. Based on these results, we show package level interconnects are well suited for power demanding low latency applications and we analyze different interconnect options like memory buses, long inter tile interconnects, clock and power distribution.

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Section: Fig 5 Fabricated Wlp Test Chip Cross Sectionmentioning

confidence: 99%

“…Specifically, interconnects at the Wafer Level Packaging layers are well suited for the global wiring applications [14].…”

Section: Fig 3 Propagation Mode Cutoff Frequencies For Different Tecmentioning

confidence: 99%