We propose improving system availability by performing in-field repair at the chip level. This enables margining and detection of degrading memory cells before the user observes any errors. A 576 Mb embedded DRAM at 1.5 GHz in a 40nm CMOS technology achieves improved resilience to both aging memory cells and cells with variable retention time (VRT). Un-interrupted user access of 6 billion 72-bit read and write operations per second is maintained during background repair. IntroductionThe common approach to memory faults is to 1) in manufacturing detect and repair hard faults with column, row, and/or block redundancy and 2) in the field to detect and correct soft errors with error correcting codes (ECC) and background scrubbing. However, studies on DRAMs in high performance computing clusters [1] and Google's servers [2] have concluded that memory errors in the field are dominated by hard faults, which cannot be fixed by scrubbing.One limitation with scrubbing, system-level solutions such as mapping out persistent errors or de-allocating substantial address ranges, and the proposed in-field architectures to date [3,4] is that they do not detect faults before errors occur. Even if the system is able to recover when an error is encountered, the error handling may cause additional latency that may not be acceptable.In the following, we first present a study of aging and VRT memory bits. We show that aging bits can change gradually. We then describe an architecture and an implementation that take advantage of this phenomenon to detect and repair weak bits in the background without affecting user access or requiring system level error handling.

A 576 Mb DRAM is implemented with 16 serial links at 10.3125Gbps. Using careful memory/SerDes/package codesign, the system achieves 14.5ns latency and 24.75GByte/s read/write bandwidth. It achieves SRAM-like random access by using logic-compatible 65nm GP embedded DRAM and small 36 Kb sub-arrays with hidden refresh.

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