A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency

Vamvakos, Socrates D.; Kleveland, B.; Sikdar, Dipak K.; Ahuja, B.K.; Lin, Haidang; Balachandran, Jayaprakash; Balakrishnan, W.; Bottelli, Aldo; Chen, J.; Chen, X.; Choi, Jong‐Min; Chopra, Rajesh; Dabral, S.; Dasari, K.; David, Ronald B.; Desai, Shaishav; Gauthier, Claude R.; Hassan, Mahmudul; Hsieh, Kuo-Chiang; Canagasaby, R.; Kumala, Jeff; Kwon, Eun-jeong; Lee, B.; Liu, M.; Mandal, Gautam; Mitra, Srinjoy; Na, B. C.; Panwar, Shivendra S.; Patel, Jagdish Suresh; Rao, Chethan; Rao, V.; Rouse, Richard; Saraf, Ritesh; Seshadri, S.; Sim, Jincheol; Szeto, C.; Wang, A.; Yeung, Jason

doi:10.1109/esscirc.2012.6341354

Cited by 2 publications

(3 citation statements)

References 11 publications

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“…We stress-tested units of 576 Mb embedded DRAM products in 65nm [5] and 40nm logic processes. The units were characterized with a wide range of retention times to detect any shift over time.…”

Section: Technology: Aging Bits and Vrtmentioning

confidence: 99%

Early detection and repair of VRT and aging DRAM bits by margined in-field BIST

Kleveland

Choi

Kumala

et al. 2014

2014 Symposium on VLSI Circuits Digest of Technical Papers

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We propose improving system availability by performing in-field repair at the chip level. This enables margining and detection of degrading memory cells before the user observes any errors. A 576 Mb embedded DRAM at 1.5 GHz in a 40nm CMOS technology achieves improved resilience to both aging memory cells and cells with variable retention time (VRT). Un-interrupted user access of 6 billion 72-bit read and write operations per second is maintained during background repair. IntroductionThe common approach to memory faults is to 1) in manufacturing detect and repair hard faults with column, row, and/or block redundancy and 2) in the field to detect and correct soft errors with error correcting codes (ECC) and background scrubbing. However, studies on DRAMs in high performance computing clusters [1] and Google's servers [2] have concluded that memory errors in the field are dominated by hard faults, which cannot be fixed by scrubbing.One limitation with scrubbing, system-level solutions such as mapping out persistent errors or de-allocating substantial address ranges, and the proposed in-field architectures to date [3,4] is that they do not detect faults before errors occur. Even if the system is able to recover when an error is encountered, the error handling may cause additional latency that may not be acceptable.In the following, we first present a study of aging and VRT memory bits. We show that aging bits can change gradually. We then describe an architecture and an implementation that take advantage of this phenomenon to detect and repair weak bits in the background without affecting user access or requiring system level error handling.

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Section: Technology: Aging Bits and Vrtmentioning

confidence: 99%

Early detection and repair of VRT and aging DRAM bits by margined in-field BIST

Kleveland

Choi

Kumala

et al. 2014

2014 Symposium on VLSI Circuits Digest of Technical Papers

View full text Add to dashboard Cite

show abstract

“…Instead, we chose to place the SerDes circuits in the middle of the die, close to the core logic, to reduce on-chip routing delay. 11 We left the package balls for the high-speed serial I/Os at the edges of the package, because this position reduces the complexity of signal escape on the board. To manage supply noise coupling, we did careful simulation followed by silicon validation.…”

Section: Codesign Of Die and Packagementioning

confidence: 99%

“…This delay consists of two memory cycles (80 UI), four core cycles (40 UI), RXþTX delay in the SerDes (24 UI), and propagation in the chip and package (0.5 ns). 11 With two eight-lane GCI ports operating at 10.3 Gbps, the BE-1 achieves high throughput for single-word read and write commands. It can do 2.06 billion reads per second or 1.03 billion writes per second.…”

Section: Latency and Access Ratementioning

confidence: 99%