and 5 highlight how relaxed gate pitch improves fT which results from not only lower capacitance from wider gate-toWe report record RF performance in 45-nm silicon-oncontact spacing but also enhanced stress response (higher insulator (SOI) CMOS technology. RF performance scaling transconductance gm) of the device. Fig. 6 shows peak fTvs. with channel length and layout optimization is demonstrated. I/Lpoly for SOI CMOS from 90 to 45-nm nodes, Peak fT's of 485 GHz and 345 GHz are measured in floatingdemonstrating that RF performance scaling continues with body NFET and PFET with nearby wiring parasitics (i.e., gateLpoly in deep sub-lOOnm CMOS technologies. Figs. 7 and 8 to-contact capacitance) included after de-embedding, thus show the gm and Cgate (= Cgs + Cgd) vs. I/Lpoly extracted at representing FET performance in a real design. The measured peak fT condition for 45-nm SOI NFETs and PFETs, fT's are the highest ever reported in a CMOS technology. Bodyindicating the well controlled channel with Lpoly. contacted FETs are also analyzed that have layout optimized Source/drain contact pitch as well as gate poly pitch can be for high-frequency analog applications. Employing a notched optimized for RF applications, and Figs. 9 and 10 show the body contact layout, we reduce parasitic capacitance and gate measuredfT and gm for minimum poly pitch SOI NFETs and leakage current significantly, thus improving RF performance PFETs with an Lp of 31 nm as a function of gate bias, with low power. For longer than minimum channel length and a where wider source/drain contact pitches result in higherfT, body-contacted NFET with notched layout, we measure a peak due to the lowering of gate-to-contact capacitance with fT of 245 GHz with no degradation in critical analog figures of fewer contacts. Note also in Figs. 9 and 10 that the gm of the merit, such as self-gain. device is not affected much by the potential increase of source/drain resistance with fewer contacts. Introduction B. Body-contacted SQL FET analog/RF Performance This high-performance 45-nm SOI technology features 1.16 nm gate oxide, dual stress liners (DSL), eSiGe PFET, advancedIn high-frequency analog circuits, device self-gain (gm activation annealing, and stress memorization techniques over output conductance gds) and matching between (SMT) [1]. Advanced immersion lithography employed neighboring devices are important. For such consideration, provides good channel length control and supports multiple we investigate SOI NFETs with longer than minimum gate pitches. To investigate the suitability of this high channel length (for high self-gain) and a body contact (for performance CMOS technology for millimeter-wave digital good matching due to reduced VBS fluctuation). Fig. 11 and analog system-on-chip (SoC) applications [2, 3, 4], Sshows the measured self-gain as a function of gate bias for a parameter measurements at frequencies up to 110 GHz were floating-body NFET with 32 nm Lp01y and body-contacted performed to analyze RF/analog characteristics of partially-NFET w...

No abstract

No abstract

Abstract-This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 temperature variation is 3 dB. At the 25 GHz center frequency, the VCO is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.

No abstract

No abstract

No abstract

No abstract