Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications

Fractional Gain Control Technique for a Low-Jitter and Area-Efficient Digital Phase-Locked Loop

“…Furthermore, the logic synthesis feature of the digital PLL reduces the design time and has better programmability, portability, and testability when the PLL is converted to different CMOS process technologies. As a result, digital PLLs have recently gained broad interest as an alternative to conventional analog charge-pump based PLLs [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15].…”

“…In recent years, the bang-bang digital PLL (BB-DPLL) has been widely researched as an attractive topology for a clock generator for SoC applications owing to its simple implementation and small area [9][10][11][12][13][14][15]. Figure 2 shows a top-level diagram of a conventional BB-DPLL.…”

“…Figure 3 shows a second-order MASH sigma-delta modulator. Dithering streams of a high-order MASH sigma-delta modulator have been widely used not only to improve the effective frequency resolution but also to remove spurious tones of the DCO [1][2][3][4][5][6][7][8][9][10][11]. However, a wide dithering range of a high-order sigma-delta modulator increases the deterministic jitter; for instance, second and third-order sigma-delta modulators have maximal dithering gain ranges of 3×d I and 5×d I , respectively [14].…”

Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter

“…The loop linearization for the case of nonaccumulative reference clock jitter (due to white phase noise) has been developed in [13] and applied to the analysis of a secondorder loop in [18]. When the reference clock jitter is small, however, the loop behaves nonlinearly, making the linear analysis inapplicable for applications where a clean reference is used [7]. Furthermore, little is known about the output-jitter performance when the reference clock is the dominant jitter source, as typically occurs in CDR applications [1].…”

Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter

“…While they are typically implemented based on the charge-pump PLL architecture [2], [3], recent progress in the development of low-noise digitally-controlled oscillators (DCOs) has resulted in several digital BBPLL (DBBPLL) implementations suitable for high-bandwidth digital frequency synthesis [4], [5].…”