2007 IEEE International Electron Devices Meeting 2007
DOI: 10.1109/iedm.2007.4418916
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Record RF performance of 45-nm SOI CMOS Technology

Abstract: and 5 highlight how relaxed gate pitch improves fT which results from not only lower capacitance from wider gate-toWe report record RF performance in 45-nm silicon-oncontact spacing but also enhanced stress response (higher insulator (SOI) CMOS technology. RF performance scaling transconductance gm) of the device. Fig. 6 shows peak fTvs. with channel length and layout optimization is demonstrated. I/Lpoly for SOI CMOS from 90 to 45-nm nodes, Peak fT's of 485 GHz and 345 GHz are measured in floatingdemonstratin… Show more

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Cited by 153 publications
(73 citation statements)
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“…Greatest enhancement comes with shortest L g , for example, L g = 20 nm and r = 12.5 nm could give 30% f T improvement and 20 dB A VO enhancement. Values of A VO in misaligned DG devices are comparable to and indeed, in some cases, better than those reported in state-of-the-art single gate SOI devices [39]. As a simple design rule for accommodating misalignment/oversize without degrading the performance, the optimum straggle values for m/L g or O/L g lying in the range 0 (self/bestaligned) to 1 (worst-aligned), are given as ðrÞ optimal ffi r o þ ðcÞ…”
Section: Impact Of Back Gate Misalignment/oversize With Gate Length Ssupporting
confidence: 73%
“…Greatest enhancement comes with shortest L g , for example, L g = 20 nm and r = 12.5 nm could give 30% f T improvement and 20 dB A VO enhancement. Values of A VO in misaligned DG devices are comparable to and indeed, in some cases, better than those reported in state-of-the-art single gate SOI devices [39]. As a simple design rule for accommodating misalignment/oversize without degrading the performance, the optimum straggle values for m/L g or O/L g lying in the range 0 (self/bestaligned) to 1 (worst-aligned), are given as ðrÞ optimal ffi r o þ ðcÞ…”
Section: Impact Of Back Gate Misalignment/oversize With Gate Length Ssupporting
confidence: 73%
“…This has been achieved by the continuous down scaling of the MOS transistors (MOSFET) geometry. This reduction has promoted the fabrication of sub-100 nm transistors and the possibility to get devices with cutoff frequencies higher than 200 GHz [1][2][3].…”
Section: Introductionmentioning
confidence: 99%
“…B Eleni Chatzikyriakou ec3g12@soton.ac.uk 1 Department of Electronics and Computer Science, University of Southampton, University Road, Southampton SO17 1BJ, UK Three-dimensional finite elements method (FEM) simulation of TID in transistor models is generally avoided due to the complexity introduced in its use. Experimental work is often complemented by the 'fixed oxide charge' method.…”
Section: Introductionmentioning
confidence: 99%
“…Thick field isolation is widely used today as a Buried OXide (BOX) in silicon-on-insulator technologies [1], as shallow trench isolation separating devices in single and multi-gate technologies [2] and it is also commonly found in 2D semiconductor transistors such as graphene and MoS 2 [3,4]. These oxides are the main contributing factor to Total Ionizing Dose (TID) effects of deep submicron technologies, contrary to the thin gate oxides, where trapped charges are able to tunnel out under the influence of the electric field [5].…”
Section: Introductionmentioning
confidence: 99%