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SUMMARYThe modeling of MOS transistors used for RF applications needs the definition of a lumped equivalent circuit where the intrinsic device and series extrinsic resistances are properly evaluated. The model accuracy depends on the extraction precision of each intrinsic lumped element. In order to determine the intrinsic device behavior, it is necessary to first remove the series extrinsic resistances. For this reason their extraction becomes critical for the modeling of MOS transistors in RF circuit design. Several extraction methods have been proposed; nevertheless, the measurement noise strongly affects the obtained results. The method proposed by Bracale and co-workers is the most robust extraction procedure against measurement noise, but fails to predict correctly the series extrinsic resistances for deep-submicron devices. For those reasons, we deeply analyze the method proposed by Bracale in order to understand and then overcome its limitations. Based on those analyses, a robust extraction method for deep-submicron devices is proposed.

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Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of the CMOS technology, thanks to their high immunity against the so-called short channel effects. However, due to their threedimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic resistances and capacitances. In this paper, based on measurements and 3-D numerical simulations we analyze the impact of the extrinsic gate capacitance on the RF behavior of FinFETs. It observes that the extrinsic capacitances are larger than the intrinsic counterparts for sub-100 nm devices. Furthermore, the reduction of the fin spacing as well as the increase of the fin geometrical aspect ratio (height/width) can improve significantly the FinFETs RF behavior.

These last years, the triple-gate fin field-effect transistor (FinFET) has appeared as attractive candidate to pursue the complementary metal-oxide semiconductor technology roadmap for digital and analog applications. However, the development of analog applications requires models that properly describe the static and RF behaviors as well as the extrinsic parameters related to the three-dimensional FinFET architecture, in order to establish adequate design strategies. We demonstrate the feasibility of the compact model developed for symmetric doped double-gate metal-oxide-semiconductor field-effect transistor (symmetric doped double-gate MOSFET) to reproduce the experimental dc and RF behaviors for 40-nm technology node Silicon-on-Insulator triple-gate FinFETs. Extrinsic gate capacitances and access extrinsic resistances have been included in order to properly predict the transistor small-signal behavior, the current gain, and the maximum available power gain cut-off frequencies. Finally, the improvement of the FinFET RF characteristics by the reduction of the parasitics is addressed. Figure 13. Comparison between the modeled (lines) and experimentally obtained (dots) maximum oscillation frequency. Figure 14. Simulated maximum oscillation frequency vs. source/drain fin extension for several values of fin spacing. 476 A. G. MARTINEZ-LOPEZ ET AL.