A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Abstract

Abstract-This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 temperature variation is 3 dB. At the 25 GHz center frequency, the VCO is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.

A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance

“…The design's VCO topology is an improvement on the linearized transconductance VCO (LiTVCO) described in [21], incorporating enhancements such as a noise bypass circuit, described in detail in Section III. To double the VCO fundamental frequency, the second harmonic frequency naturally generated in the LiTVCO is tapped at two locations: 1) the center-tap of the biasing inductor, and 2) the tail node, as shown in the figure.…”

“…The total area occupied by the PLL is mm . The VCO, amplifier and buffer complex occupies m m while the VCO alone occupies m m. As shown in the die micrograph, the implementation also includes autonomic phase noise optimization infrastructure: a peak detector, an ADC, and a DAC, similar to the infrastructure available in [21]. Additionally, as shown in Fig.…”

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion

“…After the new data {(x (n) , f NEW (n) ); n = 1, 2, …, N} are available, the new coefficients {α NEW,k ; k = 1, 2, ..., K} can be modeled by the probability density function pdf(α NEW | f NEW ) (i.e., the posterior distribution) in (7). Depending on the shape of the posterior distribution pdf(α NEW | f NEW ), the new coefficients {α NEW,k ; k = 1, 2, ..., K} do not take all possible values with equal probability.…”

“…Such a measurement task, however, is not trivial, because many analog performance metrics (e.g., phase noise) cannot be easily measured by on-chip sensors. For this reason, the idea of indirect performance sensing has been recently proposed [6]- [7] where the performance of interest (PoI) is not directly measured by an on-chip sensor. Instead, it is accurately predicted from a set of other performance metrics, referred to as the performances of measurement (PoM), that are highly correlated with PoI and are easy to measure.…”

VCO Design using NAND Gate for Low Power Application

“…Many delay cell designs are reported in literature for VCO design including multiple-feedback loops, dualdelay paths and single ended delays [11][12][13][14][15][16][17][18][19]. Performance of these delay cells largely affects the performance of VCO circuit.…”