VCO Design using NAND Gate for Low Power Application

Kumar, Manoj

doi:10.5573/jsts.2016.16.5.650

Cited by 9 publications

(3 citation statements)

References 24 publications

(21 reference statements)

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“…The obtained tuning range for this condition is 26 per cent. The presented power dissipations are also much lower than some previously presented low-power ring and CMOS LC VCOs (Rastegar et al, 2018;Azadmousavi and Aghdam, 2018;Kumar, 2016;Ebrahimzadeh, 2011). The results in Figure 5 have rising behavior for the dissipation power when the control voltage increases especially when the control voltage is above 0.5 V. This is somehow expected because increasing the oscillation frequency would result in more switching dissipation power in the transistors.…”

Section: Simulationsmentioning

confidence: 66%

Proposed 3.5 µW CNTFET-MOSFET hybrid CSVCO for power-efficient gigahertz applications

Khorram

Kokabi

2020

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Purpose Several ultra-low power and gigahertz current-starved voltage-controlled oscillator (CSVCO) circuits have been proposed and compared here. The presented structures are based on the three-stage hybrid circuit of the carbon nanotube field-effect transistors (CNTFETs) and low-power MOSFETs. The topologies exploit modified and compensated Schmitt trigger comparator parts to demonstrate better consumption power and frequency characteristics. The basic idea in the presented topologies is to compensate the Schmitt trigger comparator part of the basic CSVCO for achieving faster carrier mobility of the holes, reducing transistor leakage current and eliminating dummy transistors. Design/methodology/approach This study aims to propose and compare three different comparator-based VCOs that have been implemented using the CNTFETs. The considered circuits are shown to be capable of delivering the maximum 35 tuning frequency in the order of 1 GHz to 5 GHz. A major power thirsty part of the high-frequency ring VCOs is the Schmitt trigger stage. Here, several fast and low-power Schmitt trigger topologies are exploited to mitigate the dissipation power and enhance the oscillation frequency. Findings As a result of proposed modifications, more than one order of magnitude mitigation in the VCO power consumption with respect to the previously presented three-stage CSVCO is reported here. Thus, a VCO dissipation power of 3.5 µW at the frequency of 1.1 GHz and the tuning range of 26 per cent is observed for the well-established 32 nm technology and the supply voltage of 1 V. Such a low dissipation power is obtained around the operating frequency of the battery-powered cellular phones. In addition, using the p-carrier mobility compensation and enhancing the rise time of the Schmitt trigger part of the CSVCO, a maximum of 2.38 times higher oscillation frequency and 72 per cent wider tuning range with respect to Rahane and Kureshi (2017) are observed. Simultaneously, this topology exhibits an average of 20 per cent reduction in the power consumption. Originality/value Several new VCO topologies are presented here, and it is shown that they can significantly enhance the power dissipation of the GHz CSVCOs.

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Section: Simulationsmentioning

confidence: 66%

Proposed 3.5 µW CNTFET-MOSFET hybrid CSVCO for power-efficient gigahertz applications

Khorram

Kokabi

2020

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“…In view of the fact, that the power utilization is subsequently important for designing of any oscillator. The configuration of ring oscillator consists of a source with the same gain stages to produce periodic waveforms by a set frequency [19]. The frequency is controlled by adjusting the delay of the gain stage.…”

Section: The Static Cmos Invertermentioning

confidence: 99%

Ring Oscillator for 60 Meter Bandwidth

Arya¹,

Singh²

2023

Computer Systems Science and Engineering

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The 60-meter band range is tremendously useful in telecommunication, military and governmental applications. The I. T. U. (International Telecommunication Union) required isolationism to former radio frequency services because the various frequency bands are extremely overloaded. The allocation of new frequency bands are a lengthy procedure as well as time taking. As a result, the researchers use bidirectional, amateur radio frequency communication for 60meter band, usually the frequency slot of 5250-5450 KHz, although the entire band is not essentially obtainable for all countries. For transmission and reception of these frequencies, a local oscillator is used in the mixer unit to generate the local signal for mixing the input and reference signals. For this function different type of oscillators are used. In this paper, a three-stage ring oscillator is designed with 1 V supply. Ring oscillators (RO) is the base to explore like to identifying, specify with modelling resources in the disparity in behaviour of the circuit in terms of industrialized design and layout parameters. This type of oscillators are free from noise as inductor is not used to the circuit as in LC oscillator, Heartly oscillator, Colpitt and tuned oscillators. The present approach of circuit designing, the scaling of CMOS (Complementary Metal Oxide Semiconductor) transistor will moderate, the procedure variability. In the forthcoming article, a ring oscillator with fixed capacitor (1 pF) and with variable capacitors (1 to 100 pF) is analysed. The frequency analysis with different capacitor is performed. The total delay of 3-stage oscillator is 4.82 ns with 5.2 MHz oscillation frequency. The overall Power dissipation of the circuit is 1.852 μW at 1 V supply. The simulation analysis is performed on 45 nm CMOS technology with both transistor width are 278 and 420 nm.

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“…Figure 12: Comparison of power consumption for different VCO architecturesThe term phase noise in a VCO is used to describe the random frequency fluctuations in the signal(Kumar 2016). The stability measures the extent to which an oscillator tends to maintain a constant frequency over a period of time.…”

mentioning

confidence: 99%

Design and Implementation of High Frequency and Low-Power Phase-locked Loop

Premananda¹,

Dhanush²,

Parashar³

et al. 2021

UPjeng

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Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.

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VCO Design using NAND Gate for Low Power Application

Cited by 9 publications

References 24 publications

Proposed 3.5 µW CNTFET-MOSFET hybrid CSVCO for power-efficient gigahertz applications

Proposed 3.5 µW CNTFET-MOSFET hybrid CSVCO for power-efficient gigahertz applications

Ring Oscillator for 60 Meter Bandwidth

Design and Implementation of High Frequency and Low-Power Phase-locked Loop

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