Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion

Sun, Shouyue; Wang, F.; Yaldiz, Soner; Li, X.; Pileggi, Larry; Natarajan, Arun; Ferriss, Mark; Plouchart, J.-O.; Sadhu, Bodhisatwa; Parker, B.; Valdes‐Garcia, Alberto; Sanduleanu, Mihai; Tierno, J.; Friedman, Daniel

doi:10.1109/cicc.2013.6658489

Cited by 17 publications

(7 citation statements)

References 8 publications

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“…Based on the BMF idea in [30], since the reference wafer and the m-th wafer share a similar spatial pattern, we expect that their DCT coefficients {α t,r,k ; k = 1, 2, ..., K} and {α t,m,k ; k = 1, 2, ..., K} are similar. Such a prior knowledge can be mathematically encoded by the following prior distribution:…”

Section: A Prior Knowledge Definitionmentioning

confidence: 99%

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

Zhang

Blanton

et al. 2014

2014 International Test Conference

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In this paper, a novel Bayesian model fusion (BMF) method is proposed for test cost reduction based on waferlevel spatial variation modeling. BMF relies on the assumption that a large number of wafers of the same circuit design (e.g., all wafers from the same lot) share a similar spatial pattern. Hence, the measurement data from one wafer can be borrowed to model the spatial variation of other wafers via Bayesian inference. By applying the Sherman-Morrison-Woodbury formula, a fast numerical algorithm is derived to reduce the computational cost of BMF for practical test applications. Furthermore, a new test methodology is developed based on BMF and it closely monitors the escape rate and yield loss. As is demonstrated by the wafer probe measurement data of an industrial RF transceiver, BMF achieves 1.125× reduction in test cost and 2.6× reduction in yield loss, compared to the conventional approach based on virtual probe (VP).

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Section: A Prior Knowledge Definitionmentioning

confidence: 99%

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

Zhang

Blanton

et al. 2014

2014 International Test Conference

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“…A refinement technique based on Baysian Model Fusion is proposed in [9]. Its interesting aspect is that the refinement requires collecting few additional measurement data at each point in time.…”

Section: Calibration Principles and Pre-vious Workmentioning

confidence: 99%

One-Shot Calibration of RF Circuits Based on Non-Intrusive Sensors

Andraud

Stratigopoulos

Simeu

2014

Proceedings of the 51st Annual Design Automation Conference

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We propose a post-fabrication calibration technique for RF circuits that is performed during production testing with minimum extra cost. Calibration is enabled by equipping the circuit with tuning knobs and sensors. Optimal tuning knob identification is achieved in one-shot based on a single test step that involves measuring the sensor outputs once. For this purpose, we rely on variation-aware sensors which provide measurements that remain invariant under tuning knob changes. As an auxiliary benefit, the variation-aware sensors are non-intrusive and totally transparent to the circuit. The technique is demonstrated on a 65nm RF power amplifier.

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“…For increased frequency flexibility, highly optimized switched inductor [29] and switched capacitor [30] based LC VCOs can be utilized to obtain a wide range of frequencies without sacrificing noise performance. Moreover, on-chip self-healing techniques [31] utilizing a digital back end can be used for healing the switched capacitor circuits as well as improving the clock jitter [32].…”

Section: Nonidealitiesmentioning

confidence: 99%

Passive Switched Capacitor RF Front Ends for Spectrum Sensing in Cognitive Radios

Sadhu

Sturm

Sadler

et al. 2014

International Journal of Antennas and Propagation

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This paper explores passive switched capacitor based RF receiver front ends for spectrum sensing. Wideband spectrum sensors remain the most challenging block in the software defined radio hardware design. The use of passive switched capacitors provides a very low power signal conditioning front end that enables parallel digitization and software control and cognitive capabilities in the digital domain. In this paper, existing architectures are reviewed followed by a discussion of high speed passive switched capacitor designs. A passive analog FFT front end design is presented as an example analog conditioning circuit. Design methodology, modeling, and optimization techniques are outlined. Measurements are presented demonstrating a 5 GHz broadband front end that consumes only 4 mW power.

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Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion

Cited by 17 publications

References 8 publications

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

One-Shot Calibration of RF Circuits Based on Non-Intrusive Sensors

Passive Switched Capacitor RF Front Ends for Spectrum Sensing in Cognitive Radios

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