Modeling of Variation in Submicrometer CMOS ULSI Technologies

Springer, S.; Lee, Sung Jae; Lu, Ning; Nowak, E.; Plouchart, J.-O.; Watts, J.; Williams, R.; Zamdmer, N.

doi:10.1109/ted.2006.880165

Cited by 65 publications

(30 citation statements)

References 26 publications

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“…The ongoing shrinkage process in technology development leads to an increasing influence of process variations on circuit characteristics [27], [28]. In order to examine these influences, parametric variations, as they appear from tolerances in the manufacturing process, must be explored on the circuit level [29].…”

Section: E Circuit Simulationmentioning

confidence: 99%

Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

Lorenz

Bär

Clees

et al. 2011

IEEE Trans. Electron Devices

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Abstract-Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. In this first of two consecutive papers, sources of process variations and the state of the art of related simulation tools are reviewed. An approach for hierarchical simulation of process variations including their correlations is presented. The second paper, also published in this issue, presents examples of simulation results obtained with this methodology.

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Section: E Circuit Simulationmentioning

confidence: 99%

Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

Lorenz

Bär

Clees

et al. 2011

IEEE Trans. Electron Devices

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“…Therefore, the surface temperature is due to both radiation and conduction. However, in today's RTA process, the time duration of heating is so short (less than 1 second [11]) that complete thermal equilibrium between conduction and radiation cannot be achieved, and the surface temperature is primarily determined by the ability of different regions of the wafer to absorb heat from the RTA lamps.…”

Section: Background a Rapid Thermal Annealingmentioning

confidence: 99%

“…Therefore, STI regions absorb significantly more heat, and transistors that lie in the neighborhood of large STI density regions tend to have lower V T , because of higher local annealing temperature. Moreover, REXT in these regions is decreased due to the combination of improved dopant activation and increased gate overlap of the source and drain [11]. The impact of these effects on circuit-level performance is that the delay and leakage of these regions will differ from other regions with higher reflectivity.…”

Section: Background a Rapid Thermal Annealingmentioning

confidence: 99%

“…The effective STI density captures the effect of averaging the reflectivity over a region, and the effect of heat transfer by conduction within the wafer, and can be used as a rough predictor of local annealing temperature [11]. To make the annealing temperature uniform, dummy polysilicon fills can be inserted over the STI region to even out the effective STI density, as illustrated in Fig.…”

Section: B Dummy Polysilicon Filling For Rtamentioning

confidence: 99%

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Physical design techniques for optimizing RTA-induced variations

Wei¹,

Hu²,

Liu³

et al. 2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Abstract-At 65nm and below, Rapid Thermal Annealing (RTA) makes a significant contribution to manufacturing process variations, degrading the parametric yield. RTA-induced variability strongly depends on circuit layout patterns, particularly the distribution of the density of the Shallow Trench Isolation (STI) regions. In this work, we investigate a two-step approach to reduce the impact of RTA-induced variations. We first solve a floorplanning problem that aims to reduce the RTA variations by evening out the STI density distribution. Next, we insert dummy polysilicon fills to further improve the uniformity of the STI density. Experimental results show that our floorplanner can reduce the global RTA variations by 39% and the local variations by 29% on average with low overhead compared to a traditional floorplanner, and the proposed dummy fill algorithm can further reduce the RTA variations to negligible amounts. Moreover, when inserting dummy fills, for the layouts obtained by our floorplanner, on average, 24% fewer dummy polysilicon fills are inserted, as compared to the results from a traditional floorplanner.

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“…There have been many studies on the characterization, simulation, and modeling of such statistical variations, especially on interdie and intradie/across-chip variations and device tracking behavior in recent years [1][2][3][4][5][6][7][8][9]. In a statistical description of a process, device, or circuit's variability, one important aspect is the modeling of acrosschip variations (ACV) or device tracking in a SPICE model.…”

Section: Introductionmentioning

confidence: 99%

Modeling of Transistor's Tracking Behavior in Compact Models

2011

Active and Passive Electronic Components

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We present a novel method to model the tracking behavior of semiconductor transistors undergoing across-chip variations in a compact Monte Carlo model for SPICE simulations and show an enablement of simultaneous N(N −1)/2 tracking relations among N transistors on a chip at any poly density, any gate pitch, and any physical location for the first time. At smaller separations, our modeled tracking relation versus physical location reduces to Pelgrom's characterization on device's distance-dependent mismatch. Our method is very compact, since we do not use a matrix or a set of eigen solutions to represent correlations among N transistors.

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Modeling of Variation in Submicrometer CMOS ULSI Technologies

Cited by 65 publications

References 26 publications

Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

Physical design techniques for optimizing RTA-induced variations

Modeling of Transistor's Tracking Behavior in Compact Models

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