and 5 highlight how relaxed gate pitch improves fT which results from not only lower capacitance from wider gate-toWe report record RF performance in 45-nm silicon-oncontact spacing but also enhanced stress response (higher insulator (SOI) CMOS technology. RF performance scaling transconductance gm) of the device. Fig. 6 shows peak fTvs. with channel length and layout optimization is demonstrated. I/Lpoly for SOI CMOS from 90 to 45-nm nodes, Peak fT's of 485 GHz and 345 GHz are measured in floatingdemonstrating that RF performance scaling continues with body NFET and PFET with nearby wiring parasitics (i.e., gateLpoly in deep sub-lOOnm CMOS technologies. Figs. 7 and 8 to-contact capacitance) included after de-embedding, thus show the gm and Cgate (= Cgs + Cgd) vs. I/Lpoly extracted at representing FET performance in a real design. The measured peak fT condition for 45-nm SOI NFETs and PFETs, fT's are the highest ever reported in a CMOS technology. Bodyindicating the well controlled channel with Lpoly. contacted FETs are also analyzed that have layout optimized Source/drain contact pitch as well as gate poly pitch can be for high-frequency analog applications. Employing a notched optimized for RF applications, and Figs. 9 and 10 show the body contact layout, we reduce parasitic capacitance and gate measuredfT and gm for minimum poly pitch SOI NFETs and leakage current significantly, thus improving RF performance PFETs with an Lp of 31 nm as a function of gate bias, with low power. For longer than minimum channel length and a where wider source/drain contact pitches result in higherfT, body-contacted NFET with notched layout, we measure a peak due to the lowering of gate-to-contact capacitance with fT of 245 GHz with no degradation in critical analog figures of fewer contacts. Note also in Figs. 9 and 10 that the gm of the merit, such as self-gain. device is not affected much by the potential increase of source/drain resistance with fewer contacts. Introduction B. Body-contacted SQL FET analog/RF Performance This high-performance 45-nm SOI technology features 1.16 nm gate oxide, dual stress liners (DSL), eSiGe PFET, advancedIn high-frequency analog circuits, device self-gain (gm activation annealing, and stress memorization techniques over output conductance gds) and matching between (SMT) [1]. Advanced immersion lithography employed neighboring devices are important. For such consideration, provides good channel length control and supports multiple we investigate SOI NFETs with longer than minimum gate pitches. To investigate the suitability of this high channel length (for high self-gain) and a body contact (for performance CMOS technology for millimeter-wave digital good matching due to reduced VBS fluctuation). Fig. 11 and analog system-on-chip (SoC) applications [2, 3, 4], Sshows the measured self-gain as a function of gate bias for a parameter measurements at frequencies up to 110 GHz were floating-body NFET with 32 nm Lp01y and body-contacted performed to analyze RF/analog characteristics of partially-NFET w...

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In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology computer-aided design-based statistical modeling. Compared with planar SOI high-k metal gate CMOS technologies, 14-nm SOI FinFET technology shows better n-to-p tracking mainly due to the strong influence of correlated Fin geometrical variation, as well as reduced uncorrelated variation from an innovative work function process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/fast and fast/slow corners in certain conditions and, therefore should be considered in guard time design.Index Terms-Integrated circuits design, MOSFETs, semiconductor device modeling, variation aware timing. 0018-9383

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