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The time dependence of hot carrier degradation of n-channel MOSFETs and the methodology of accelerated stress have been investigated in detail. The time (T) dependence is foLund to be inconsistent with the simple expression of TN (N 0.25 ), but rather slhow a slow-down of the degradation rate. The slope of the degradation curve is also found to be dependent on the stress bias voltage. The projection of device lifetime by accelerated stress based on the TN law and the assumption of constant slope independent of stress bias is unreliable.

Specific contact resistivities of the Al/TiW/TiSiz/Si system are characterized. It is found that without a TiW barrier layer, AI can penetrate through the TiSi2 layer and significantly affect the TiSiz/Si interfacial contact resistance. Intrinsic TiSil contact resistivities to n+ and p+ silicon are characterized with a TiW barrier between the silicide and the aluminum. TiSiz contact resistivity to n + silicon is found to be about one order of magnitude lower than that of AI to n * silicon. However, Ti& to p * silicon contact resistivity is higher than that of AI to p + silicon and is very sensitive to the boron implant dose. 0 1 1 1 8

A new substrate and gate current phenomenon in short-channel LDD and minimum overlap devices has been observed. This phenomenon is well characterized experimentally by studying devices with different gate oxide thickness, spacer width, and n-region doping. A good physical understanding is obtained by using a two-dimensional device simulation program together with experimental data analysis. This effect can be maximized for use as a potential low-voltage EPROM or avoided for reliability reason by properly designing the n-region doping, gate overlap, and oxide spacer width.

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Ah.ftracl -We p resent un unomll]OUS llltchup 1:1ilure phellllmenon related to the large Nwcll resistor associated with the gcnerie RC -triggered. MOSFET -based Active Clamp cireui! for on-chip ESD protection between VCC and VSS hus�s. 1\ nm'el Active Clamp circuit with PMOS fecdback tcchnique has been proposed to reduce the Ie's 'lI,ccptihilit�· tll Latchup during negativc current injection at ncig.hboring 1/0 pads or false triggering of the RC trigger circuit due to noise on the VCC power line. The cffccti\'eness of this ncw Actiyc Chlmp circuit is contirmed b�' our e"periment and simulation results, Optimisation of tllc size of the PMOS feedback transistor is also discussed in thi,; pa p er.