Active ESD shunt with transistor feedback to reduce latchup susceptibility or false triggering

Abstract

Ah.ftracl -We p resent un unomll]OUS llltchup 1:1ilure phellllmenon related to the large Nwcll resistor associated with the gcnerie RC -triggered. MOSFET -based Active Clamp cireui! for on-chip ESD protection between VCC and VSS hus�s. 1\ nm'el Active Clamp circuit with PMOS fecdback tcchnique has been proposed to reduce the Ie's 'lI,ccptihilit�· tll Latchup during negativc current injection at ncig.hboring 1/0 pads or false triggering of the RC trigger circuit due to noise on the VCC power line. The cffccti\'eness of this ncw Actiyc Chlmp circuit is contirmed b�' our e"periment and simulation results, Optimisation of tllc size of the PMOS feedback transistor is also discussed in thi,; pa p er.

Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test

“…However, the large RC time constant used in the power-rail ESD clamp circuit may cause false triggering during a fast power-up condition with a rise time of less than 10 s. The modified power-rail ESD clamp circuit incorporated with PMOS feedback, as shown in Fig. 2(b), was used to mitigate such a mistrigger problem [6]. The transistor MPFB can help to keep the gate voltage of ESD-clamping NMOS below its threshold voltage and further reduce the current drawn during the power-up condition.…”

Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology

“…In general, the n-well resistance is usually regarded as an optimal choice in the RC-based ESD-transient detection circuit to obtain an adequate resistance and a sufficient RCtime delay. A few electrons would be captured by this n-well resistance since this n-well resistance could be performed as the guard ring of the minority to capture the minority carriers (electrons) in the p-substrate [17]. Although the n-well resistance has been surrounded by the N+/n-well minority guard rings connecting to VDD, some escaped electrons were still captured by the n-well resistance to induce the voltage drop between the two terminals of the n-well resistance in the design with 3-stage inverters and BFT.…”