Scaling limitations of submicron local oxidation technology

Hui, J.; Voorde, Paul Vande; Moll, J.L.

doi:10.1109/iedm.1985.190983

Cited by 23 publications

(9 citation statements)

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“…This effect was first seen by Hui et al (1). For instance, the scaling of local oxidation of silicon (LOCOS) isolation into the 0.25 ~m regime requires altering the isolation stack to reduce encroachment for small active areas.…”

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confidence: 92%

Field Oxide Thinning in Poly Buffer LOCOS Isolation with Active Area Spacings to 0.1 μm

Lutze

Perera

Krusius

1990

J. Electrochem. Soc.

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Field oxide thinning in a modified LOCOS process is examined. Using electron beam lithography, thinning in active area spacings as narrow as 0.1 ~m has been observed for the first time. Also, the cause of thinning is shown to be compressive stress in the field oxide, not two-dimensional oxidant diffusion as has been previouslY asserted. A phenomenological model for field oxide thinning is given. Finally, a new figure of merit is defined which assesses the combined effects of encroachment and field oxide thinning in isolation processes for submicron integrated circuits.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 130.237.29.138 Downloaded on 2015-03-08 to IP

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confidence: 92%

Field Oxide Thinning in Poly Buffer LOCOS Isolation with Active Area Spacings to 0.1 μm

Lutze

Perera

Krusius

1990

J. Electrochem. Soc.

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“…In device isolation processes, the local oxidation of silicon (LOCOS) isolations has already reached the scaling limit because of the bird's beak, crystal defects and field-oxide-thinning phenomena. 1,2) Currently, the trench isolation technology is considered an effective method for overcoming such problems and for improving the integration level of quarter-micron devices. 3,4) Also, to fabricate high-performance devices, the diffused well should be replaced by the retrograde well using the high-energy ion implantation technology.…”

Section: Introductionmentioning

confidence: 99%

Composition and Electrical Properties of Metallic Ru Thin Films Deposited Using Ru(C₆H₆)(C₆H₈) Precursor

Choi

Hong

et al. 2002

Jpn. J. Appl. Phys.

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The effectiveness of denudation annealing at high temperatures on the characteristics of ultra large-scale integration (ULSI) devices has been studied. The secondary-ion mass spectroscopy (SIMS) profile showed that the oxygen atoms near the wafer surface diffuse out during the denudation anneal and the amount of outdiffused oxygen atoms increases with the increase of denudation annealing temperature. The depth of the defect-free zone (DFZ) at the surface region, the breakdown property of the thin gate oxide of 7 nm thickness and the leakage current of PN junction diodes were greatly improved following by the denudation annealing process at a high temperature. It is found that the refresh properties of a 256 Mbit dynamic randomaccess memory (256 M-DRAMs) were closely related to the depth of the DFZ at the device surface and were improved by the denudation annealing. Therefore, denudation annealing at high temperatures is effective for the fabrication of reliable quarter-micron level DRAM devices.

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“…However, it is well-known that a bird's beak reduction is often accompanied by process-induced silicon defects (17), because silicon stresses increase with an increase of the slope of the field oxide interface near its edge. Hence, to reveal possible crystallographic defects in silicon, the initial test structures were stripped to bare silicon and decorated with Wright (18) and Secco (19) etches.…”

Section: Resultsmentioning

confidence: 99%

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

Ghezzo

Kaminsky

Nissan-Cohen

et al. 1989

J. Electrochem. Soc.

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Local oxidation of polysilicon over silicon (tOPOS) isolation has been characterized for use in a 0.8 ~m CMOS/BULK process with reduced field oxide edge encroachment (bird's beak). Compared to the standard local oxidation of silicon (LOCOS) LOPOS adds a thin polysilicon layer between the stress relief oxide and the overlying nitride without changing the active area patterning procedure. To optimize the LOPOS structure, the thickness of the oxide and nitride layers was varied in a fully-factorial experiment, measuring the bird's beak and checking for the presence of silicon edge defects. It was found }hat for a 6000A field oxide the bird's beak can be safely reduced to =0.3 I~m per side with tOPOS, which is significantly less than =0.55 ~m with LOCOS. The corresponding stack consisted of 1500,~ Si3N4/550A polysilicon (undoped)/ 200A SiO2. LOPOS fabricated diodes exhibited low leakage of <0.5 nA/cm 2 and <0.5 pA/cm for the area and edge components, respectively, while MOS capacitors were breakdown-free up to 8 MV/cm during voltage-stress tests, compared to 6 MV/cm for LOCOS. ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 157.182.150.22 Downloaded on 2015-04-12 to IP

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Scaling limitations of submicron local oxidation technology

Cited by 23 publications

References 0 publications

Field Oxide Thinning in Poly Buffer LOCOS Isolation with Active Area Spacings to 0.1 μm

Field Oxide Thinning in Poly Buffer LOCOS Isolation with Active Area Spacings to 0.1 μm

Composition and Electrical Properties of Metallic Ru Thin Films Deposited Using Ru(C₆H₆)(C₆H₈) Precursor

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

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Scaling limitations of submicron local oxidation technology

Cited by 23 publications

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Field Oxide Thinning in Poly Buffer LOCOS Isolation with Active Area Spacings to 0.1 μm

Field Oxide Thinning in Poly Buffer LOCOS Isolation with Active Area Spacings to 0.1 μm

Composition and Electrical Properties of Metallic Ru Thin Films Deposited Using Ru(C6H6)(C6H8) Precursor

LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

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Composition and Electrical Properties of Metallic Ru Thin Films Deposited Using Ru(C₆H₆)(C₆H₈) Precursor