Abstract-A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital-analog converter waveform asymmetry and a higher tolerance to clock imperfections. The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs.
This paper presents a powerful automated license plate recognition system, which is able to read license numbers of cars, even under circumstances, which are far from ideal. In a real-life test, the percentage of rejected plates was 13%, whereas 0.4% of the plates were misclassified. Suggestions for further improvements are given.
This research work proposes new concepts of flexibility and self-correction for current-steering digital-to-analog converters (DACs) which allow the attainment of broad functional and performance specifications, high linearity, and reduced dependence on the fabrication processes.This work analytically investigates the DAC linearity with respect to the accuracy of the DAC unit elements. The main novelty of the proposed approach is in the application of the Brownian Bridge (BB) process to precisely describe the DAC Integrated-Non-Linearity (INL). The achieved results fill a gap in the general understanding of the most quoted DAC specification-the INL.Further, this work introduces a classification of the highly diverse current-steering DAC correction methods. The classification automatically points to methods that do not exist yet in the open literature (gaps). Based on the clues of the common properties and identified common techniques in the introduced classification, this work then proposes exemplary solutions to fill in the identified gaps.Further, this work systematically analyses self-calibration correction methods for the DAC mismatch errors. Their components are analyzed as three building blocks: self-measurement, error processing algorithm and self-correction block. This work systemizes their alternative implementations and the associated tradeoffs. The findings are compared to the available solutions in the literature. The efficient calibration of the DAC binary currents is identified as an important missing method. This work proposes a new methodology for correcting the mismatch errors of both the nominally identical unary and the scaled binary DAC currents.Further, this work proposes a new concept for DAC flexibility. This concept is realized in a new flexible DAC architecture. The architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, flexible functionality and flexible performance. The parallel sub-DAC units form a mixedsignal platform that is capable of many DAC correction methods, including calibration, error mapping, data reshuffling, and harmonic distortion cancellation.This work presents the implementation and measurement results of three DAC test-chip implementations in 250 nm, 180 nm, and 40 nm standard CMOS IC technologies. The test-chips are used as a tool to practically investigate, validate, and demonstrate two main concepts of this book: self-calibration and flexibility.Particularly, the 180 nm test-chip is the first reported DAC implementation that calibrates the errors of all its current sources and features flexibility, as suggested in this work. The calibration of all current sources makes the DAC accuracy independent of the tolerances of the manufacturing process. The overall DAC accuracy depends on a single design parameter-the correction step. The third test-chip is the first reported DAC implementation in 40 nm CMOS process. A 12 bit DAC core in this test-chip occupies only 0.05 mm 2 of silicon area, which is the smallest repo...
This paper presents an 11b 1GS/s ADC with a parallel sampling architecture to enhance SNDR for broadband multi-carrier signals. It contains two 1GS/s 11b sub-ADCs each achieving > 54dB SNDR for input frequencies up to Nyquist frequency and state-of-the-art linearity performance. The SNDR of the ADC with the parallel sampling architecture is improved by 5dB compared to its sub-ADCs when digitizing multi-carrier signals with large crest factors. This improvement is achieved at less than half the cost in power and area compared to the conventional approach. The chip is implemented in 65nm LP CMOS and consumes in total 350mW at 1GS/s.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.