Sigma-delta modulators operating at a limit cycle

Abstract

Abstract-A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital-analog converter waveform asymmetry and a higher tolerance to clock imperfections. The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs.

Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators

“…It has however been shown in previous publications ( [7,11,13]) that introducing a controlled oscillation does not necessarily render the modulator useless, but instead can offer some attractive properties. Firstly, the SOSDM's loop operates at the oscillation frequency instead of the sampling frequency, (which is always significantly higher).…”

5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025mm²

“…It consists of a loop filter H(s), a comparator clocked at f s , a single-bit feedback DAC and a digital delay of d clock cycles. In [7] a similar system is presented, except for the fact that a hysteresis based comparator is used to induce self-oscillation in the Σ∆ loop. However, the rest of the analysis made there remains valid for the delaybased modulator.…”

A selectable-bandwidth 3.5 mW, 0.03 mm2 self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth

“…Since 3-bit quantization corresponds to 8 PWM-levels, the clock frequency f s2 of the PWM Σ∆ modulator should be 8 times higher than the carrier frequency f C and hence 4 times higher than the original clock frequency [1].…”

“…In this case, we want that the output of the loop consists of a stable and well-controlled self-oscillation. In [1], it was shown that a stable self-oscillation will occur at the frequency f c where the phase shift of the overall loop gain equals 180 • . Obviously part of this phase shift will occur in the loop filter while the rest of the phase shift occurs due to the delay in the loop.…”

“…This equation uses the factor (d + 1 2 ) and not just d because the zero-order-hold DAC-pulse also gives half a clock cycle delay, which was neglected in other work [1].…”