An on-chip self-calibration method for current mismatch in D/A converters

Radulov, Georgi; Quinn, Patrick; Hegt, Hans; Roermund, Arthur van

doi:10.1109/esscir.2005.1541586

Cited by 27 publications

(13 citation statements)

References 13 publications

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“…As compared to traditional post-fabrication mismatch calibration method, such as in [7,16], the ESES method can provide very fine tuning resolution without the need of implementing very small calibration units which can be challenging and costly in some applications. For example, implementing small current sources for current steering DAC calibration leads to large area overhead of calibration units [16].…”

Section: Extended Statistical Element Selection (Eses)mentioning

confidence: 99%

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A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

2016

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Section: Extended Statistical Element Selection (Eses)mentioning

confidence: 99%

“…For example, implementing small current sources for current steering DAC calibration leads to large area overhead of calibration units [16]. Another problem of traditional post-fabrication calibration method is the missing calibration codes.…”

Section: Extended Statistical Element Selection (Eses)mentioning

confidence: 99%

A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

2016

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“…However, the most widely used design technique is the current steering type [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] because it has the capability of driving resistive loads without any special buffers, such as operational amplifiers, and is suitable for simple CMOS implementation. Further, it provides high-speed operation and its power consumption is low in comparison with the other types.…”

Section: Introductionmentioning

confidence: 99%

Design of a laminated current cell relocation 12-bit CMOS D/A converter with a high output impedance technique and a merged switching logic

Moon

Song

Shin³

et al. 2009

Analog Integr Circ Sig Process

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A compact and low power 12-bit 300 MS/s current steering CMOS D/A converter is presented. The architecture of the D/A converter is based on the current steering 6 ? 6 segmented type with a laminated current cell relocation technique. In order to improve the linearity and glitch noise, a high output impedance analog current cell is designed. Furthermore, for the purpose of reducing the chip area and power dissipation, a noble merged switching logic and a compact layout technique are proposed. To verify its performance, the chip was fabricated with 0.13 lm thick-gate 1-poly 6-metal N-well Samsung CMOS technology. The effective chip area is 0.26 mm 2 (510 9 510 lm) with a power consumption of 100 mW. The measured INL and DNL are within ±3LSB and ±1LSB, respectively. The measured SFDR is about 70 dB, when the input frequency is 1 MHz at a clock frequency of 300 MHz.

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“…For the calibration of the unary current cells, the reference consists of the sum of all binary current cells and one LSB current source as in [7]. Therefore, the binary current cells should be calibrated before the unary current cell calibration.…”

Section: ) Unary Current Cellsmentioning

confidence: 99%

“…The ADC does not need to be fast or accurate and is implemented as a Successive Approximation (SAR) ADC [6], [7] with 5 bits linearity. The additional area for the ADC and the FSM is negligible compared to the area of the current source array.…”

Section: ) Unary Current Cellsmentioning

confidence: 99%