A novel temperature and disturbance insensitive DAC calibration method

Bechthum, Elbert; Radulov, Georgi; Roermund, Arthur van

doi:10.1109/iscas.2011.5937988

Cited by 9 publications

(6 citation statements)

References 8 publications

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“…This paper extends upon [13] and our previous work [16], and presents a two-step coarse-fine calibration algorithm applied to a 9-bit 5-GS/s current-steering DAC in 90-nm CMOS technology. The calibration utilizes that the random mismatch distribution in many DAC designs tends to be zero mean and symmetric, which is our underlying assumption in developing the calibration algorithm.…”

Section: Introductionmentioning

confidence: 72%

“…As a slightly different approach, Bechthum et al [13] presented an idea of adding redundant unit cells in the weight groups in a conventional current steering DAC. Because each weight group has redundant unit current cells, these exist multitude of possible subsets that can be chosen to form a desired weight group.…”

Section: Introductionmentioning

confidence: 99%

“…Because each weight group has redundant unit current cells, these exist multitude of possible subsets that can be chosen to form a desired weight group. Behavioral simulations in [13] showed that choosing an appropriate subset out of possible combinations having redundancy can yield substantial DC linearity improvement. In comparison with aforementioned resequencing methods, the fixed association of DAC inputs with groups of unit cells results in less flexibility in assigning unit cells to desired weight groups.…”

Section: Introductionmentioning

confidence: 99%

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A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters

Kim

Modjtahedi

Yang

2015

IEEE Trans. VLSI Syst.

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This paper presents a highly digital calibration technique suitable for high-speed digital-to-analog converters (DACs). The proposed calibration method does not require an adjustment of on-chip analog voltages and can therefore be a favorable method in a deeply scaled nanometer process. The calibration utilizes that adding several redundant unit current cells to predetermined weight groups can be achieved with low hardware overhead, and choosing the best subset out of multitude of combinations leads to accuracy improvement. This paper proposes a two-step coarse-fine algorithm to choose the best subset for weight groups and analyzes the design tradeoff between the amount of redundancy and the expected yield via numerical simulations. To verify the proposed calibration method, a prototype 9-bit current-steering DAC has been implemented in 90-nm CMOS technology. The calibration algorithm is implemented as software to expedite the experiment. The measured results show that static linearity performance improves by 10.8× when the proposed calibration technique is applied. When running the DAC at 5-GS/s sampling speed, similar performance improvement has been observed, achieving peak signal-to-noise-distortion ratio of 54 dB at low frequency and 8-bit linearity when generating sinusoid up to 1 GHz.

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Section: Introductionmentioning

confidence: 72%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters

Kim

Modjtahedi

Yang

2015

IEEE Trans. VLSI Syst.

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“…Examples of smart methods are: amplitude calibration [17][18][19], timing error calibration [20,21], Sub-DAC harmonic cancellation [22], RDmodulation [2] or predistortion. Although these smart methods can improve specific non-idealities, the correction mechanisms can introduce or deteriorate other non-idealities, e.g.…”

Section: Smart Methodsmentioning

confidence: 99%

Classification for synthesis of high spectral purity current-steering mixing-DAC architectures

Bechthum

Radulov

Briaire³

et al. 2015

Analog Integr Circ Sig Process

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This paper proposes a classification of Mixing-DAC architectures, focusing on spectral purity. Based on literature research, analysis and simulations, the proposed classification shows the impact of architectural choices on the output spectral purity. To concretize the classification and validate the analysis, a number of specific Mixing-DAC architectures are synthesized, discussed and simulated. Given the proposed classification, a set of optimal architectural choices lead to a strong architecture candidate for achieving high spectral purity at high signal frequencies, i.e. SFDR [ 80 dBc at f OUT = 4 GHz for current and future multicarrier GSM applications. The main characteristics of this architecture are: Cartesian signaling, local Gilbert-cell mixing and a fully differential implementation.

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“…error sources 7-9) are not discussed in this paper. Other authors have extensively discussed these effects [17]- [20]. Moreover, the DAC-function non-linearities are common to global mixing and local mixing.…”

Section: E Dac Non-idealitiesmentioning

confidence: 99%

Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM

Bechthum

Radulov

Briaire

et al. 2012

2012 IEEE International Symposium on Circuits and Systems

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A novel temperature and disturbance insensitive DAC calibration method

Cited by 9 publications

References 8 publications

A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters

A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters

Classification for synthesis of high spectral purity current-steering mixing-DAC architectures

Systematic analysis of the impact of mixing locality on Mixing-DAC linearity for multicarrier GSM

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