Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption

A highly linear CMOS transconductance amplifier in 180 nm process technology

“…[12] (measured) along with a wide linear input range of 1.2 V pp for 1% transcoductance variation which is around 600 mV (approximated from the waveforms) only in the structures designed and simulated in [10], clearly outperforms the previously reported linearized differential pair based transconductors.…”

“…The distortion, noise and other performances of the proposed transconductor are comparable with the reference architectures in Table 2. Table 3 provides more relevant comparison of the distortion performance of the proposed structure with the architectures in [10] as all the designs have been simulated using 180 nm CMOS process technology. In the proposed configuration -70 dB HD3 is achieved for 600 mV, 5 MHz differential input signal Ref.…”

“…In comparison to the cross coupled structures (CCP, RDP, RCCP) in [10] where the output current noise is the summation of two cross-coupled differential pairs with large degeneration resistors, the noise performance of the proposed OTA (ARDP) is quite comparable with the existing structures.…”

“…Moreover with the technology scaling these circuit solutions are becomimg more complex and consume more power to achieve the desired performance. In [10] an improved linearized transconductor based on simple differential pair with cross-coupling and resistive source degeneration (RCCP) has been proposed and the performance is compared with some of the previous works like resistor degenerated differential pair (RDP) and cross-coupled differential pairs (CCP). All the circuit topologies (which were designed in higher process technology and published before) were re-designed and simulated in 180 nm CMOS process technology and compared in [10].…”

“…In [10] an improved linearized transconductor based on simple differential pair with cross-coupling and resistive source degeneration (RCCP) has been proposed and the performance is compared with some of the previous works like resistor degenerated differential pair (RDP) and cross-coupled differential pairs (CCP). All the circuit topologies (which were designed in higher process technology and published before) were re-designed and simulated in 180 nm CMOS process technology and compared in [10]. Total harmonic distortion (THD) of -80 dB for 400 mV pp input signal was achieved using resistor degenerated cross-coupled differential pairs (RCCP).…”