An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals

Abstract

This paper presents an 11b 1GS/s ADC with a parallel sampling architecture to enhance SNDR for broadband multi-carrier signals. It contains two 1GS/s 11b sub-ADCs each achieving > 54dB SNDR for input frequencies up to Nyquist frequency and state-of-the-art linearity performance. The SNDR of the ADC with the parallel sampling architecture is improved by 5dB compared to its sub-ADCs when digitizing multi-carrier signals with large crest factors. This improvement is achieved at less than half the cost in power and area compared to the conventional approach. The chip is implemented in 65nm LP CMOS and consumes in total 350mW at 1GS/s.

Improving dynamic range of software‐defined radio receivers for multi‐carrier wireless systems

“…Afterwards, in [18], a similar design has been evaluated by several simulations for Gaussian distributed signals demonstrating an improvement of about 8 dB in the achievable dynamic range. This paper has been further validated in [19] by realising a parallel sampling architecture on a 65 nm CMOS chip, being evaluated with sinusoidal and multi-carrier 256-quadrature amplitude modulation (QAM) modulated signals, showing improvements of 5 dB for the multi-carrier situation. In addition, in [20] a novel reconstruction scheme based on a gain weighted combining approach has been applied on top of the same parallel ADC architecture.…”

“…Instead of a power splitter plus an attenuator [4] or a resistive divider [19], in this paper a directional coupler is utilised because it would maintain good noise figure for the entire receiving chain (lower loss is expected in the mainline), which for RF wideband applications wherein the ADC component is placed as close as possible to the beginning of the receiving chain, and the influence on the overall noise figure would be much lower. In addition, other points could be raised such as in terms of power dissipation that is much stressful for resistive devices.…”

Implementations of the Parallel-Sampling ADC Architecture

“…Therefore, these ADCs are normally thermal noise limited. Circuit techniques for maximizing signal swing are commonly adopted for the purpose of minimizing sampling capacitor sizes [21,22,25,26,29,30,32,33]. Figure 4.10 shows a TI SAR ADC architecture (with hierarchical T/Hs) which is a suitable architecture for designing GHz sampling rate and medium-to-high resolution ADCs [21,22].…”

Power-Efficient High-Speed Parallel-Sampling ADCs for Broadband Multi-carrier Systems

“…However, the reduction of the sampling capacitor makes the ADC easier to drive and doesn't affect the overall power efficiency [15,22,33] and the required large output signal swing of the ADC driver can be achieved by using the mixed-supply-voltage approach without compromising the speed as proposed in [26,27]. Firstly, while this architecture is intended to improve the ADC power efficiency for multi-carrier signals that have a 'bell-shaped' amplitude probability distribution function (e.g.…”

“…ADCs with GHz sampling rate and medium-to-high resolution (SNR > 50 dB) are mostly based on time-interleaving architecture nowadays [21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36]. In these ADCs, small sampling capacitors and transistors with low parasitic capacitance are desired in order to achieve high signal bandwidth and low power consumption.…”