Smart and Flexible Digital-to-Analog Converters

Abstract

This research work proposes new concepts of flexibility and self-correction for current-steering digital-to-analog converters (DACs) which allow the attainment of broad functional and performance specifications, high linearity, and reduced dependence on the fabrication processes.This work analytically investigates the DAC linearity with respect to the accuracy of the DAC unit elements. The main novelty of the proposed approach is in the application of the Brownian Bridge (BB) process to precisely describe the DAC Integrated-Non-Linearity (INL). The achieved results fill a gap in the general understanding of the most quoted DAC specification-the INL.Further, this work introduces a classification of the highly diverse current-steering DAC correction methods. The classification automatically points to methods that do not exist yet in the open literature (gaps). Based on the clues of the common properties and identified common techniques in the introduced classification, this work then proposes exemplary solutions to fill in the identified gaps.Further, this work systematically analyses self-calibration correction methods for the DAC mismatch errors. Their components are analyzed as three building blocks: self-measurement, error processing algorithm and self-correction block. This work systemizes their alternative implementations and the associated tradeoffs. The findings are compared to the available solutions in the literature. The efficient calibration of the DAC binary currents is identified as an important missing method. This work proposes a new methodology for correcting the mismatch errors of both the nominally identical unary and the scaled binary DAC currents.Further, this work proposes a new concept for DAC flexibility. This concept is realized in a new flexible DAC architecture. The architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, flexible functionality and flexible performance. The parallel sub-DAC units form a mixedsignal platform that is capable of many DAC correction methods, including calibration, error mapping, data reshuffling, and harmonic distortion cancellation.This work presents the implementation and measurement results of three DAC test-chip implementations in 250 nm, 180 nm, and 40 nm standard CMOS IC technologies. The test-chips are used as a tool to practically investigate, validate, and demonstrate two main concepts of this book: self-calibration and flexibility.Particularly, the 180 nm test-chip is the first reported DAC implementation that calibrates the errors of all its current sources and features flexibility, as suggested in this work. The calibration of all current sources makes the DAC accuracy independent of the tolerances of the manufacturing process. The overall DAC accuracy depends on a single design parameter-the correction step. The third test-chip is the first reported DAC implementation in 40 nm CMOS process. A 12 bit DAC core in this test-chip occupies only 0.05 mm 2 of silicon area, which is the smallest repo...

Digital-to-Analog Converters

“…The fastest architecture of the commercially available DACs is the current steering DAC [2,3] as shown in Fig. 7.4.…”

A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme

“…Note that the threshold mismatch of the switch transistors M sw is transferred to timing mismatch errors via the slope of the switching signals. Thus, sharp edges are required for small timing errors among the D/A cells [13]. This advantage of the CMOS drivers reduces when the capacitive self-loading effects dominate, e.g., in the case of reduced power supply.…”

“…Finally, for more than 3-bits of unary segmentation, the complexity of the binary-to-unary decoder increases which may become critical in terms of power consumption at high sampling rates. A more in-depth discussion about the segmentation strategies can be found in [13]. Thus, three MSB of unary segmentation is considered as a good tradeoff between area, decoder complexity and MSB data transition matching.…”

“…Since the maximum allowable transistor width and length may be limited by the process to about 0.9 µm, a unit current source is implemented as two parallel structures of two stacked transistors. Such sizes with conventional layout techniques are expected to easily guarantee 6-bits static intrinsic linearity yield, according to [13], [18]- [20]. Moreover, as no cascodes are used, more voltage headroom is allocated for the current source transistor, allowing a high overdrive voltage and hence reduced V th mismatch.…”

A novel timing-error based approach for high speed highly linear Mixing-DAC architectures

“…For high linearity at high frequency, both timing and amplitude of the 1-bit cells should be considered. The amplitude matching in CS (Mixing-)DACs has been thoroughly researched, and many intrinsic and correction methods exist [4]. However, the synthesis of a Mixing-DAC architecture with the focus on timing errors is not discussed in open literature, while this is critical for achieving high linearity at high frequency.…”