A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme

Radulov, Georgi; Quinn, Patrick; Roermund, Arthur van

doi:10.1109/tvlsi.2014.2298055

Cited by 21 publications

(13 citation statements)

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“…Moreover, they show better power supply rejection and lesser data-dependent ripple on the power supply. However, the reduced swing results in a larger slope for the data transitions, which may lead to larger timing errors [59]. CML drivers are also found to be less power efficient than CMOS [18].…”

Section: Switch Driver Designmentioning

confidence: 99%

“…LVDS which increases the pin count. Since DACs are being increasingly embedded in complex SOCs, on-chip DFT features are also required to enable faster testing [59]. One of the ways to do this is to integrate digital sine generators (or digital frequency synthesizers) on chip.…”

Section: Dac Testing Challengesmentioning

confidence: 99%

“…Memories facilitate flexible testing as any test pattern can be loaded into them. High-speed embedded memories to enable full-speed testing have been reported in a few previous works [7,49,59]. The depth of the memory is determined by the spacing between two nearest frequency bins that is desired.…”

Section: Dac Testing Challengesmentioning

confidence: 99%

“…2.36(a). This style is very popular with relatively larger memory sizes for high speeds and has been previously used in [7] and [59]. An additional advantage of using the styles of Figs.…”

Section: Dac Testing Challengesmentioning

confidence: 99%

“…An additional advantage of using the styles of Figs. 2.36(b) and 2.36(c) is that power supply noise and substrate noise introduced is largely data independent as all the flips-flops are a part of shift register that operates every clock [59]. This property makes them of interest in mixed signal designs.…”

Section: Dac Testing Challengesmentioning

confidence: 99%

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Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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Section: Switch Driver Designmentioning

confidence: 99%

Section: Dac Testing Challengesmentioning

confidence: 99%

Section: Dac Testing Challengesmentioning

confidence: 99%

“…2.36(a). This style is very popular with relatively larger memory sizes for high speeds and has been previously used in [7] and [59]. An additional advantage of using the styles of Figs.…”

Section: Dac Testing Challengesmentioning

confidence: 99%

Section: Dac Testing Challengesmentioning

confidence: 99%

See 3 more Smart Citations