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The design and electro-optical measurements of a 25 Gbit/s common cathode vertical cavity surface-emitting laser (VCSEL) driver in 90 nm bulk CMOS technology is presented. The driver is bonded to a 14 Gbit/s commercial VCSEL providing both DC and modulation current to the laser. The power consumption including the VCSEL is 60 mW. Since the DC bias of the VCSEL exceeds the breakdown voltage of thin oxide transistors, a novel output stage configuration using isolated wells is proposed. The active area is only 127 × 50 μm.Introduction: Development of information technology constantly increases the demand for interconnects with extremely high data rates. The dramatic increases of connection density introduces challenges due to power consumption issues and electromagnetic interferences [1]. On one hand, technology scaling reduces mass production costs, power consumption and increases the computational performance of the core circuits. On the other hand, inter-chip electrical connections continue to be restricted by the physical limits of the electrical channels [2]. One possible solution is the use of power-efficient optical interconnects as their frequency-dependent loss is negligible; they allow a high data rate and they are not affected by electrical crosstalk [3]. A costefficient implementation of these links is the use of a directly modulated vertical cavity surface-emitting laser (VCSEL) controlled by a driver circuit in a low-cost CMOS technology. In this case, the laser driver can be integrated in one system with the core chip, thus avoiding multichip packaging costs and performance deterioration. The commercial availability of more than 25 Gbit/s VCSELs is increasing, their power dissipation and costs are low and VCSELs are good candidates for the implementation of low-power optical interconnects [3]. One of the fastest available VCSELs to date has a bandwidth of 26 GHz [4]. Since VCSELs emit light vertically, with two-dimensional arrays multiple parallel 25 Gbit/s optical channels can be realised [5] as defined in the future Ethernet Standard 802.3bs. This Letter presents a practical implementation and the measurement results of a low-power, high-speed common cathode VCSEL driver in CMOS technology. The driver is very compact and can be easily integrated with the serialiser and re-timer circuit removing the 50 Ω input resistance used only for the measurement purposes.

The measurement results and a practical application of vertical inductors (VIs) are presented. VIs are on-chip inductors designed to save chip area. In VI the spiral plane is oriented perpendicularly with respect to the substrate. An inductance of 318 pH with a self-resonance frequency of 66.5 GHz is implemented in a 130 nm bipolar complementary metal-oxide semiconductor (BiCMOS) technology and results are compared with three-dimensional (3D) planar EM (ground-signal-ground) simulations. The inductance per unit area is 424 nH/mm 2 , more than 1.7 times higher than other simulated spiral horizontal inductors. Moreover, VIs have been applied in the design of a broadband amplifier leading to a 25% bandwidth enhancement.

Optimizing a modulator driver for linear and high-speed operation, while simultaneously achieving a high output voltage swing is very challenging. This paper investigates the design of a highlylinear, high-bandwidth yet power-efficient Mach-Zehnder modulator driver based on the breakdown voltage doubler concept, which overcomes the transistors' physical limitations and enables output voltage swings twice as high as conventional differential pair amplifiers can provide. The low-power design was enabled by the use of an open-collector topology for the output stage as well as by employing resistors instead of current mirrors in order to provide the bias currents for the emitter-follower (EF) stages. We show that by means of this EF implementation approach, the power consumption can be reduced by 19% without sacrificing the circuit's bandwidth and linearity. The driver achieves peak-to-peak differential output voltage swings above 6.5 V pp,d and consumes 670 mW of DC power, being one of the most power-efficient drivers in the literature. The 3-dB bandwidth is 61.2 GHz and the total harmonic distortion is 1%, measured at 1 GHz and for the output swing of 6.5 V pp,d . To the best of the authors' knowledge, these are the highest linearity and output voltage swing reported in the literature for modulator drivers with bandwidths above 40 GHz.INDEX TERMS breakdown voltage doubler, linear broadband amplifier, fiber-optic communication, high voltage swing, low THD, Mach-Zehnder modulator (MZM), modulator driver, SiGe BiCMOS