Common cathode VCSEL driver in 90 nm CMOS enabling 25 Gbit/s optical connection using 14 Gbit/s 850 nm VCSEL

Abstract

The design and electro-optical measurements of a 25 Gbit/s common cathode vertical cavity surface-emitting laser (VCSEL) driver in 90 nm bulk CMOS technology is presented. The driver is bonded to a 14 Gbit/s commercial VCSEL providing both DC and modulation current to the laser. The power consumption including the VCSEL is 60 mW. Since the DC bias of the VCSEL exceeds the breakdown voltage of thin oxide transistors, a novel output stage configuration using isolated wells is proposed. The active area is only 127 × 50 μm.Introduction: Development of information technology constantly increases the demand for interconnects with extremely high data rates. The dramatic increases of connection density introduces challenges due to power consumption issues and electromagnetic interferences [1]. On one hand, technology scaling reduces mass production costs, power consumption and increases the computational performance of the core circuits. On the other hand, inter-chip electrical connections continue to be restricted by the physical limits of the electrical channels [2]. One possible solution is the use of power-efficient optical interconnects as their frequency-dependent loss is negligible; they allow a high data rate and they are not affected by electrical crosstalk [3]. A costefficient implementation of these links is the use of a directly modulated vertical cavity surface-emitting laser (VCSEL) controlled by a driver circuit in a low-cost CMOS technology. In this case, the laser driver can be integrated in one system with the core chip, thus avoiding multichip packaging costs and performance deterioration. The commercial availability of more than 25 Gbit/s VCSELs is increasing, their power dissipation and costs are low and VCSELs are good candidates for the implementation of low-power optical interconnects [3]. One of the fastest available VCSELs to date has a bandwidth of 26 GHz [4]. Since VCSELs emit light vertically, with two-dimensional arrays multiple parallel 25 Gbit/s optical channels can be realised [5] as defined in the future Ethernet Standard 802.3bs. This Letter presents a practical implementation and the measurement results of a low-power, high-speed common cathode VCSEL driver in CMOS technology. The driver is very compact and can be easily integrated with the serialiser and re-timer circuit removing the 50 Ω input resistance used only for the measurement purposes.

20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

“…However, this technique is sensitive to start-up sequences and might breakdown on transient peaks. The LDD placed in a triple-well topology is implemented and further developed [11, 25].…”

“…A totem-pole structure is used for the output stage as it can be seen in Fig. 7(b), in order to achieve an increased efficiency as in [11, 17, 25]. Since many of the commercial VCSELs have 50 Ω impedance, the driver stage should have an output impedance of 50 Ω for an efficient power transfer.…”

Integrated Circuits for 3D Photonic Transceivers

“…The driver published in [5] provides the bias voltage and current to the VCSEL. Since the bias voltage of the VCSEL exceeds the breakdown voltage of the thin-oxide transistors, the driver is realized using isolated wells.…”

A 15 Gbps-NRZ, 30 Gbps-PAM4, 120 mA laser diode driver implemented in 0.15-µm GaAs E-mode pHEMT technology

“…These techniques improve the speed, especially when a high driving current capability is required. PAM4 driver ICs were also reported for low current vertical-cavity surface-emitting lasers (VCSELs), at 90 Gbps [20] and 56 Gbps [21] in SiGe BiCMOS technology and 25 Gbps in 90 nm CMOS [22] , and high current distributed feedback (DFB) laser, at 30 Gbps in the 65 nm CMOS process [11] .…”