Abstract-This paper focuses on commonalities and differences between the two mixed-signal hardware description languages VHDL-AMS and Verilog-AMS in the case of modeling heterogeneous or multi-discipline systems. The paper has two objectives. The first one consists of modeling the structure and the behavior of an airbag system using both the VHDL-AMS and the Verilog-AMS languages. Such a system encompasses several time abstractions (i.e. discrete-time and continuous-time), several disciplines, or energy domains (i.e., electrical, thermal, optical, mechanical, and chemical), and several continuous-time description formalisms (i.e., conservative-law and signal-flow descriptions). The second objective is to discuss the results of the proposed modeling process in terms of the descriptive capabilities of the VHDL-AMS and Verilog-AMS languages and of the generated simulation results. The tools used are Advance-MS from Mentor Graphics for VHDL-AMS and AMS Simulator from Cadence Design Systems for Verilog-AMS. The paper shows that both languages offer effective means to describe and simulate multi-discipline systems, although using different descriptive approaches. It also highlights current tool limitations since full language definitions are not yet supported.

International audienceThe paper presents an innovative simulation scheme to speed-up simulations of multi-clusters multi-processors SoCs at the TLM/T (transaction level model with time) abstraction level. The hardware components of the SoC architecture are written in standard SystemC. The goal is to describe the dynamic behavior of a given software application running on a given hardware architecture (including the dynamic contention in the interconnect and the cache effects), in order to provide the system designer with the same reliable timing information as a cycle accurate simulation, with a simulation speed similar to a TLM simulation. The key idea is to apply parallel discrete event simulation (PDES) techniques to a collection of communicating SystemC SC-THREAD. Experimental results show a simulation speedup of a factor up to 50 versus a BCA simulation (bus cycle accurate), for a timing error lower than $10^{-3}$

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International audienceThis paper presents a new compact model for the undoped, long-channel double-gate (DG) MOSFET under symmetrical operation. In particular, we propose a robust algorithm for computing the mobile charge density as an explicit function of the terminal voltages. It allows to greatly reduce the computation time without losing any accuracy. In order to validate the analytical model, we have also developed the 2D simulations of a DG MOSFET structure and performed both static and dynamic electrical simulations of the device. Comparisons with the 2D numerical simulations give evidence for the good behaviour and the accuracy of the model. Finally, we present the VHDL-AMS code of the DG MOSFET model and related simulation results

A paradigm shift is apparent in Chip Multiprocessor (CMP) design, as the new performance bottleneck is becoming communication rather than computation. It is widely provisioned that number of cores on a single chip will reach thousands in a decade. Thus, new high rate interconnects such as optical or RF have been proposed by various researchers. However, these interconnect structures fail to provide essential requirements of heterogeneous on-chip traffic; bandwidth reconfigurability and broadcast support with a low complex design. In this paper we investigate the feasibility of a new Orthogonal Frequency Division Multiple Access (OFDMA) RF interconnect for the first time to the best of our knowledge. In addition we provide a novel dynamic bandwidth arbitration and modulation order selection policy, that is designed regarding the bimodal on-chip packets. The proposed approach decreases the average latency up to 3.5 times compared to conventional static approach.

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In microelectronics, the design of new systems is based on a proven time-tested design flow. The goal of this paper is to determine to what extend this design flow can be adapted to biosystem design. The presented methodology is based on a top-down approach and consists of starting with a behavioral description of the system to progressively refine it to its final low-level system representation, composed of DNA parts. To preserve accuracy and simplicity, the design flow relies on refined models of biological mechanisms, which can be expressed by the hardware description languages and simulation tools traditionally used in microelectronics. A case study, the complete modeling of a priority encoder, is presented to demonstrate the effectiveness of the method.

International audienceWith the growing number of cores on chips, conventional electrical interconnects reach scalability limits, leading the way for alternatives like Radio Frequency (RF), optical and 3D. Due to the variability of applications, communication needs change over time and across regions of the chip. To address these issues, a dynamically reconfigurable Network on Chip (NoC) is proposed. It uses RF and Orthogonal Frequency Division Multiple Access (OFDMA) to create communication channels whose allocation allows dynamic recon-figuration. We describe the NoC architecture and the distributed mechanism of dynamic allocation. We study the feasibility of the NoC based on state of the art components and analyze its performances. Static analysis shows that, for point to point communications, its latency is comparable with a 256-node electrical mesh and becomes lower for wider networks. A major feature of this architecture is its broadcast capacity. The RF NoC becomes faster with 32 nodes, achieving a ×3 speedup with 1024. Under realistic traffic models, its dynamic reconfigurability provides up to ×6 lower latency while ensuring fairness