A paradigm shift is apparent in Chip Multiprocessor (CMP) design, as the new performance bottleneck is becoming communication rather than computation. It is widely provisioned that number of cores on a single chip will reach thousands in a decade. Thus, new high rate interconnects such as optical or RF have been proposed by various researchers. However, these interconnect structures fail to provide essential requirements of heterogeneous on-chip traffic; bandwidth reconfigurability and broadcast support with a low complex design. In this paper we investigate the feasibility of a new Orthogonal Frequency Division Multiple Access (OFDMA) RF interconnect for the first time to the best of our knowledge. In addition we provide a novel dynamic bandwidth arbitration and modulation order selection policy, that is designed regarding the bimodal on-chip packets. The proposed approach decreases the average latency up to 3.5 times compared to conventional static approach.
International audienceWith the growing number of cores on chips, conventional electrical interconnects reach scalability limits, leading the way for alternatives like Radio Frequency (RF), optical and 3D. Due to the variability of applications, communication needs change over time and across regions of the chip. To address these issues, a dynamically reconfigurable Network on Chip (NoC) is proposed. It uses RF and Orthogonal Frequency Division Multiple Access (OFDMA) to create communication channels whose allocation allows dynamic recon-figuration. We describe the NoC architecture and the distributed mechanism of dynamic allocation. We study the feasibility of the NoC based on state of the art components and analyze its performances. Static analysis shows that, for point to point communications, its latency is comparable with a 256-node electrical mesh and becomes lower for wider networks. A major feature of this architecture is its broadcast capacity. The RF NoC becomes faster with 32 nodes, achieving a ×3 speedup with 1024. Under realistic traffic models, its dynamic reconfigurability provides up to ×6 lower latency while ensuring fairness
International audience— This paper introduces flexible radio techniques inside integrated circuits in order to tackle the interconnect issue for many-core chips. We propose to take benefits from OFDMA for a RF-interconnect associated to a carrier allocation policy and adaptive modulation. A 20 GHz bandwidth is shared between 32 tilesets made of 32 tiles of 4 cores each, for a 4096 cores chip. We adopt a cognitive radio approach in order to dynamically share 1024 carriers, which avoids inter-cluster communication contention and decreases latency compared to conventional static approaches
With the growing number of cores per processor, onchip communications are becoming a critical issue. Conventional wired mesh Networks-on-Chips (NoC) are reaching their scalability limit, paving the way for new interconnect technologies such as Radio Frequency (RF), Optics and 3D. This paper presents a new routing mechanism based on the WiNoCoD architecture, a hierarchical RF interconnect with dynamic bandwidth allocation for Chip Multi Processors (CMP). WiNoCoD consists of three levels of hierarchy with an RF NoC at the highest level, a wired mesh NoC and a crossbar at the lowest level. In this paper, we propose a new organisation for the manycore supporting the RF-NoC, and introduce a new routing algorithm that can choose between wired and RF networks in order to optimize the use of RF. We show that the new architecture improves performance in terms of latency and saturation. Platform simulations show a latency reduction for lower transaction rates of up to 10% compared to the original WiNoCoD architecture and up to 30% compared to a wired mesh NoC. Furthermore, smart routing pushes back the saturation threshold up to 20%.
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