In this paper we size a RF intra-chip communications based on Orthogonal Frequency Division Multiple Access (OFDMA) modulation which allows data rate and message recipient reconfiguration. Firstly, we present the advantages of this modulation such as providing flexible and high-speed data transmission. Then, we study the impact of the RF-interconnect channel shape on the transmission in terms of required transmission power. Finally, we present the effect of the channel composed of the line and its multiple access on the transfer of information and we perform a channel equalization to overcome this undesired effect.
A paradigm shift is apparent in Chip Multiprocessor (CMP) design, as the new performance bottleneck is becoming communication rather than computation. It is widely provisioned that number of cores on a single chip will reach thousands in a decade. Thus, new high rate interconnects such as optical or RF have been proposed by various researchers. However, these interconnect structures fail to provide essential requirements of heterogeneous on-chip traffic; bandwidth reconfigurability and broadcast support with a low complex design. In this paper we investigate the feasibility of a new Orthogonal Frequency Division Multiple Access (OFDMA) RF interconnect for the first time to the best of our knowledge. In addition we provide a novel dynamic bandwidth arbitration and modulation order selection policy, that is designed regarding the bimodal on-chip packets. The proposed approach decreases the average latency up to 3.5 times compared to conventional static approach.
This paper presents a new radio frequency channel access method to a radio frequency (RF) interconnect for intra‐chip communications. The method overcomes the undesired effects that come from multiple connections in classical methods. It is based on an active access, through transistors associated in a distributed topology. This leads to better properties in terms of reflection and transmission coefficients along the transmission line. This approach is validated by making a deep comparison with the basic existing access methods (eg, direct and capacitive). Measurements on a test circuit using the 0.25 μm SiGe BiCMOS technology confirm the good performance of the proposed access.
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