Abstract-This paper focuses on commonalities and differences between the two mixed-signal hardware description languages VHDL-AMS and Verilog-AMS in the case of modeling heterogeneous or multi-discipline systems. The paper has two objectives. The first one consists of modeling the structure and the behavior of an airbag system using both the VHDL-AMS and the Verilog-AMS languages. Such a system encompasses several time abstractions (i.e. discrete-time and continuous-time), several disciplines, or energy domains (i.e., electrical, thermal, optical, mechanical, and chemical), and several continuous-time description formalisms (i.e., conservative-law and signal-flow descriptions). The second objective is to discuss the results of the proposed modeling process in terms of the descriptive capabilities of the VHDL-AMS and Verilog-AMS languages and of the generated simulation results. The tools used are Advance-MS from Mentor Graphics for VHDL-AMS and AMS Simulator from Cadence Design Systems for Verilog-AMS. The paper shows that both languages offer effective means to describe and simulate multi-discipline systems, although using different descriptive approaches. It also highlights current tool limitations since full language definitions are not yet supported.

This paper presents and discusses the foundations on which the analog and mixed-signal extensions of Sys-temC, named SystemC-AMS, will be developed. First, requirements from targeted application domains are identified. These are then used to derive design objectives and related rationales. Finally, some preliminary seed work is presented and the outline of the analog and mixed-signal extensions development work is given.

Systems-on-Chip (SoCs)

SystemC will become more and more important for the design of digital circuits from the specification down to the RT-Level. However complex systems containing also analog components. This paper introduces concepts for the extension of the SystemC methodology for the specification and design of analog and mixed signal systems. The concepts will be illustrated on a telecommunication system including digital hard-and software, analog filter and an analog environment. MotivationSystemC supports a wide range of Models of Computation (MoC) and is very well suited for the design and refinement of HW/SW-systems from functional down to register transfer level. However, for a broad range of applications the digital parts and algorithms interact with analog parts and the continuous-time environment. Due to the complexity of these interactions and the importance of the analog parts in the global system's behavior, it is essential to include the analog parts in the design process of an Analog and Mixed Signal system. Simulation performance is therefore very crucial -especially for the analog parts that usually require more detailed models than the digital parts. Thus, different and specialized analog simulators must be introduced to permit the use of the most efficient simulator for the considered application and level of abstraction. In this paper, we describe a design methodology based on analog and mixed-signal extensions of SystemC, .a.k.a. SystemC-AMS. We also illustrate the methodology with a signal processing dominated application example. SystemC OverviewSystemC is a hardware description language for discrete-time (digital) systems. This language is a subset of the object oriented programming language C++, so SystemC descriptions can be compiled, executed and debugged using standard C++ tools. In comparison to languages like VHDL or Verilog, SystemC supports an arbitrary number of Models of Computation (MoC) which allows an efficient development of executable specifications at high abstraction levels and an order of magnitude faster simulation for abstract models.The SystemC 2.0 [1] methodology combines features of existing HDL's, object oriented techniques and new methodologies for the design and refinement of digital hardware and software systems. This methodology is strongly inspired by the communication model introduced by Gajski [6]. In this methodology, modules, which consists of other modules or algorithms (sequential assignments) implemented in methods, communicates via channels. A set of methods for communication is specified in an interface. These methods are implemented in a channel. Modules can call methods of a channel, and events in a channel can activate methods in a module connected to the channel. This concept is generic enough to describe systems using various models of computation, including static and dynamic multirate dataflow networks, Kahn process networks, communicating sequential processes, and discrete events (the MoC of Verilog and VHDL). We call such systems discrete systems. Prede...

Abstract-Systems on chip are more and more heterogeneous and include software, analog/RF and digital hardware, and non-electronic components such as sensors or actuators. The design and the verification of such systems require appropriate modeling means to deal with the increasing complexity and to achieve efficient simulation. SystemC is providing a modeling and simulation framework that supports digital (discrete) hardware and software systems from abstract specifications to register transfer level models. In the paper, we are proposing a way to extend the capabilities of SystemC to support mixed discrete-continuous systems by implementing a synchronous dataflow (SDF) model of computation (MoC). The SDF MoC is used to embed continuous-time behavior in SDF modules and to support the synchronization with the existing SystemC kernel. The paper presents an overview of the architecture and the syntax of the proposed extensions and gives modeling examples with simulation results.