&lt;title&gt;Model of an instrumented optoelectronic transmission system in HDL-A and VHDL-AMS&lt;/title&gt;

Uhring, Wilfried; Hervé, Y.; Pêcheux, François

doi:10.1117/12.368465

Cited by 3 publications

(14 citation statements)

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“…As one can see, the VHDL-AMS equations of lines 31 to 40 perfectly match the physical equations (1) to (3). (1) library ieee_proposed; (2) use ieee_proposed.energy_systems.all; (3) use ieee_proposed.electrical_systems.all; (4) use ieee_proposed.mechanical_systems.all; (5) (6) entity cap_sensor is (7) generic ( (8) --mechanical properties (9) M : mass := 0.16*NANO; --seismic mass (10) D : damping := 4.0*MICRO; --damping coefficient (11) K : stiffness := 2.6455; --spring stiffness (12) --geometrical properties (13) A : real := 2.0*MICRO*110.0*MICRO; --capacitor area (14) D0: real := 1.5*MICRO); --initial position (15) port ( (16) terminal tmass, tmref : translational; (17) terminal tetop, temid, tebot: electrical); (18) end entity cap_sensor; (19) (20) architecture bhv of cap_sensor is (21) --branch quantities (22) quantity cd_pos across cd_force through tmass to tmref; (23) quantity vtm across itm through tetop to temid; (24) quantity vbm across ibm through tebot to temid; (25) --free quantities (26) quantity cd_vel: velocity; --comb drive velocity (27) quantity dtm, dbm: displacement; --comb drive displacements (28) quantity ctm, cbm: capacitance; --capacitances (29) begin ( …”

Section: ) Vhdl-ams Descriptionmentioning

confidence: 99%

“…(1) library ieee; (2) use ieee.std_logic_1164.all; (3) (4) library ieee_proposed; (5) use ieee_proposed.electrical_systems.all; (6) (7) entity trigger is (8) generic ( (9) VOAMPL : voltage := 2.5; --output voltage amplitude (10) ICLKPER: time := 20 us; --internal clock period (11) NPULSES: natural := 10; --#pulses to count (12) TT : real := 100.0e-9 --output transition time (13) ); (14) port ( (15) signal din : in std_logic; (16) terminal tp, tm: electrical (17) ); (18) end entity trigger; (19) (20) architecture bhv of trigger is (21) (22) signal intclk: std_logic := '0'; (23) signal sout : real := 0.0; (24) (25) quantity vout across iout through tp to tm; (26) (27) begin (28 …”

Section: ) Vhdl-ams Descriptionmentioning

confidence: 99%

“…`timescale 100ns/1ns (2) `include "disciplines.h" (3) (4) module trigger (din, tp); (5) input din; (6) inout tp; (7) wire din; (8) electrical tp; (9) (10) parameter real VOAMPL = 2.5; // output voltage amplitude (11) parameter ICLKPER = 200; // internal clock period (12) parameter real NPULSES = 10; // #pulses to count (13) parameter real TT = 100n; // output transition time (14) (15) reg intclk; (16) integer count; (17) real sout; (18) (19) initial begin (20) intclk = 0; (21) count = 0; (22) sout = 0; (23) end (24) (25) always #(ICLKPER/2) intclk = !intclk; (26) (27) always @(posedge din or negedge intclk) (28) begin (29) if ( …”

Section: ) Verilog-ams Descriptionmentioning

confidence: 99%

“…Note that all terminal potentials are defined relatively to the bulk terminal, a specificity of the EKV MOST model. (12) ); (13) port ( (14) terminal tin, tout, tvdd, tvss: electrical; (15) terminal tjn, tjp : thermal (16) ); (17) end entity cmos_inv; (18) (19) architecture str of cmos_inv is (6) entity mos is (7) generic ( --temperature coefficients (20) TCV : real := 1.5*MILLI; --temp. coef, of thres.…”

Section: ) Vhdl-ams Descriptionmentioning

confidence: 99%

“…`include "mos_ekv_simple.v" (4) (5) module cmos_inv (tin, tout, tjn, tjp, tvdd, tvss); (6) (7) inout tin, tout, tjn, tjp, tvdd, tvss; (8) electrical tin, tout, tvdd, tvss; (9) thermal tjn, tjp; (10) (11) parameter real WP = 60u; (12) parameter real WN = 30u; (13) parameter real LP = 0.15u; (14) parameter real LN = 0.15u; (15) (16) mos_ekv #(.MTYP(-1.0), (17) .WEFF(WP), (18) .LEFF(LP), (19) .VT0(-0.4), (20) .TCV(-1.5m)) (21) mp (.td(tout), (22) .tg(tin), (23) .ts(tvdd), (24) .tb(tvdd), (25) .tj(tjp)); (26) (27) mos_ekv #(.MTYP(1.0), (28) .WEFF(WN), (29) .…”

Section: ) Verilog-ams Descriptionmentioning

confidence: 99%

See 4 more Smart Citations

VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems

Pêcheux

Lallement²,

Vachoux

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

166

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Abstract-This paper focuses on commonalities and differences between the two mixed-signal hardware description languages VHDL-AMS and Verilog-AMS in the case of modeling heterogeneous or multi-discipline systems. The paper has two objectives. The first one consists of modeling the structure and the behavior of an airbag system using both the VHDL-AMS and the Verilog-AMS languages. Such a system encompasses several time abstractions (i.e. discrete-time and continuous-time), several disciplines, or energy domains (i.e., electrical, thermal, optical, mechanical, and chemical), and several continuous-time description formalisms (i.e., conservative-law and signal-flow descriptions). The second objective is to discuss the results of the proposed modeling process in terms of the descriptive capabilities of the VHDL-AMS and Verilog-AMS languages and of the generated simulation results. The tools used are Advance-MS from Mentor Graphics for VHDL-AMS and AMS Simulator from Cadence Design Systems for Verilog-AMS. The paper shows that both languages offer effective means to describe and simulate multi-discipline systems, although using different descriptive approaches. It also highlights current tool limitations since full language definitions are not yet supported.

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