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The present investigation aims at providing a reliable evaluation of the geometric and radiometric accuracy of the airborne Daedalus-Coastal Zone Color Scanner (CZCS), through cal/val techniques. To this aim, on November 2014, we accomplished a remote sensing campaign over the Peligna Valley (Italy). Together with the personnel of the III Nucleo Aereo of the Italian Coast Guard, based at the Pescara Airport, we deployed the Daedalus AA1268EM1 CZCS scanner on board the fixed-wing aircraft type ATR42MP and a ASD FieldSpec spectroradiometer for a simultaneous field survey. We used vicarious calibration and secondary non-parametric geometric correction to achieve absolute atmospheric correction and geometric calibration, respectively. Although the validation and calibration targets used in this study were similar in nature, correlation coefficients of the prediction equations between at-sensor radiance and ground reflectance were > 0.90 for each of the 10 CZCS wavebands and the independent error assessment demonstrate that the empirical line method can be applied to correct CZCS imagery with satisfactory results. ARTICLE HISTORY

Signal processing in ultra-wide bandwidths is one of the key challenges in the design of multi-Gb/s wireless transceivers at mm-Waves, where channels covering 57GHz to 66GHz are specified. Further considering spreads due to process variations and the stringent reference phase noise to ensure signal integrity calls for an ultra-wide tuning range and low-noise on-chip oscillator. Meeting this target is even more challenging when adopting an ultra-scaled CMOS technology node where key passive components suffer from a reduced quality factor (Q) [1]. In a 32nm node the thickness of metals closer to the substrate is half that in a 65nm process leading, for example, to MOM capacitors with roughly half Q. The penalty is only marginally compensated by the higher transistor f t , improved only by ~20%. Various techniques exploiting alternative tuning implementations have been published recently. Magnetic tuning methods where the equivalent tank inductance is varied through reflection of the secondary coil impedance of a transformer demonstrate outstanding tuning ranges but at the cost of a severe trade-off with tank Q and poor noise FOMs [2,3]. A bank of capacitors switched in and out in an LC tank is the most popular tuning approach [4][5][6]. However the quality factor is severely degraded, when large ranges are involved. In this work, the switched-capacitor tank of the VCO shown in Fig. 20.3.1 is centered around two different resonance frequencies by splitting the inductor through the switch M sw . In particular, an up-shift is produced when the switch is off due to its parasitic capacitance. The frequency range is significantly increased without compromising tank Q leading to large tuning range and high FOM simultaneously. Prototypes of the VCO have been realized in 32nm CMOS showing the following performances: 31.6% frequency tuning range, minimum phase noise of -118dBc/Hz at 10MHz offset from 40GHz with 9.8mW power dissipation. Despite being realized in an ultra-scaled 32nm standard digital CMOS process without RF thick metal options, the oscillator shows state-of-the-art performances.To gain insight into the advantages of the proposed technique, Fig. 20.3.2 shows a simplified equivalent circuit of an oscillator with the traditional switched-tankcapacitor C T approach and the proposed alternative consisting of a switch in series with the inductor L T . The negative resistance models the active devices while C fix , comparable or even larger than C T at mm-Waves, represents the fixed capacitance loading the tank, introduced primarily by parasitics of the negative resistance and buffer. When the switch is on, the two tanks have the same resonance frequency of 1/(2π(L T (C fix +C T )) 1/2 ).On the other hand, for the same switch parasitic capacitance c sw , the introduced technique leads to a much higher frequency jump. In fact c sw appears in series with C T +C fix instead of C T only, determining a larger variation of the equivalent tank capacitance. In the ultimate assumption of c sw <

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In this brief, we propose a 60 GS/s high-linearity two-stage 8 × 8 time-interleaved track-and-hold circuit where it is possible to tune the static non-linearities of the second-stage buffer by applying a proper bias voltage. This allows us to maximize the static linearity of the buffer or introduce effects that counterbalance the non-linearities of other blocks of the analog front-end. To validate the proposed circuit, a prototype in TSMC 5 nm technology is designed and a linearity calibration loop is proposed for a Pulse Amplitude Modulation SerDes receiver. For the analog buffer, circuit-level simulations are performed in Cadence Virtuoso, while the calibration loop is simulated in MATLAB. The optimal bias voltage value can be found by modeling the track-and-hold linearity using a Taylor series and implementing the linearity calibration loop in MATLAB. By applying this result to the circuit-level simulation, we obtain a total harmonic distortion of over 50 dB, which matches with the maximum value achievable across the complete bias voltage control range. Lastly, the linearity of the system is also verified using a PAM-8 pseudorandom stream signal.

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