A Track-and-Hold Circuit with Tunable Non-Linearity and a Calibration Loop for PAM-8 SerDes Receivers

Abstract

In this brief, we propose a 60 GS/s high-linearity two-stage 8 × 8 time-interleaved track-and-hold circuit where it is possible to tune the static non-linearities of the second-stage buffer by applying a proper bias voltage. This allows us to maximize the static linearity of the buffer or introduce effects that counterbalance the non-linearities of other blocks of the analog front-end. To validate the proposed circuit, a prototype in TSMC 5 nm technology is designed and a linearity calibration loop is proposed for a Pulse Amplitude Modulation SerDes receiver. For the analog buffer, circuit-level simulations are performed in Cadence Virtuoso, while the calibration loop is simulated in MATLAB. The optimal bias voltage value can be found by modeling the track-and-hold linearity using a Taylor series and implementing the linearity calibration loop in MATLAB. By applying this result to the circuit-level simulation, we obtain a total harmonic distortion of over 50 dB, which matches with the maximum value achievable across the complete bias voltage control range. Lastly, the linearity of the system is also verified using a PAM-8 pseudorandom stream signal.

A 60GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers

“…To deal with this problem, we use the buffer topology depicted in Figure 3. The simple gm-gm topology is improved by varying the diode nonlinearity through the voltage v corr , as in [8]. An optimal value of the gate voltage can be chosen to minimize the distortions of the front end.…”

“…Their combined s parameters matrix (s ch ) filters the transmitted symbols and then feeds them to the two stages TH. In the analytical discussion of the model, the input-output characteristics that reflect the buffers' static distortions were modeled using a Taylor polynomial [8,11,12], which depended on v corr in the second stage. For validation, the actual circuit was used.…”

“…With the reduction in the supply voltage in advanced technology nodes, the circuits increment their compressing behavior on the signal (lower total harmonic distortion (THD)) for the same dynamic range, needed to maintain a valid signal-to-noise Ratio (SNR). In Figure 1, (a) the symbol error rate (SER) and (b) the mean square error (MSE) are plotted to the varying SNR for various analog front-end (AFE) THD obtained through a MATLAB model of a PAM-8 receiver, as in [8]. The THD represents the static nonlinearities modeled with a Taylor approximation of the components' input-output characteristics.…”

“…The scope of this paper is to find a TI-TH circuit capable of achieving through calibration a receiver THD of the order of 50dB across different PVT conditions to maximize the performance of a PAM-8 receiver (RX). Here, we show the TI sampler presented in [8] using an improved and simpler calibration loop compared to the cited one, where the complexity scales with the number of nonnegligible residual ISI pre-and post-cursors, and a gain error can introduce a component that does not let the system set to the desired value. The proposed loop uses an algorithm that eliminates the errors given by the gain and residual ISI while having a fixed complexity.…”

“…The proposed loop uses an algorithm that eliminates the errors given by the gain and residual ISI while having a fixed complexity. Furthermore, this improved calibration was implemented in cadence virtuoso with a Verilog-A model, and its performance was verified via co-simulation with the analog circuit, while in [8] MATLAB, modeling of the analog was used.…”