A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHz

Ghilioni, Andrea; Decanis, Ugo; Monaco, Enrico; Mazzanti, Andrea; Svelto, F.

doi:10.1109/isscc.2011.5746319

Cited by 21 publications

(8 citation statements)

References 3 publications

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“…Recently, inductorless divider designs employed the CML family or True-Single-Phase-Clock (TSPC) logic family to increase the speed. Several design examples can be found in the literature [15]- [19].…”

Section: State Of the Artmentioning

confidence: 99%

Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology

Özsema

Kostak

Demirci

et al. 2015

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &Amp; International Symposium on System-on-Chip (SoC)

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Abstract-In this paper we present the design of a programmable frequency divider in 28 nm FD-SOI CMOS technology. It consists of the cascade of a divide-by-2 cell and divideby-2/3 blocks. The final circuit is capable of dividing by even numbers between 128 and 254. The forward-body-bias property of the process and the differential-cascode voltage-switch-logic (DCVSL) family are used to achieve high operation speed. The proposed circuit achieves a maximum operating frequency of 20 GHz at 1 V supply voltage. And the area and the power consumption of the programmable divider are 1815 µm 2 and 4.35 mW, respectively.

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Section: State Of the Artmentioning

confidence: 99%

Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology

Özsema

Kostak

Demirci

et al. 2015

2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &Amp; International Symposium on System-on-Chip (SoC)

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“…Based on the simulated results, the tuning range of the VCO is from 24.7 to 27.25 GHz, which can cover the desired operation of 25.088 GHz for the PLL. The ring-based injection-locked /4 divider [15] is employed for the first stage to reduce the area of the PLL. The divider can function in a frequency range from 19 to 27 GHz with a 200-mV signal injection based on the simulation.…”

Section: Pllmentioning

confidence: 99%

A K-Band Reconfigurable Pulse-Compression Automotive Radar Transmitter in 90-nm CMOS

Tan

Chu

et al. 2015

IEEE Trans. Microwave Theory Techn.

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A K-band ultra-wideband (UWB) pulse-compression (PC) automotive radar transmitter in 90-nm CMOS is presented, which is composed of the fully integrated pulse generator, mixer, driver amplifier, phase-locked loop, and timing circuitry. The PC technique with coding gain can effectively enhance the detection resolution and also improve the signal-to-noise ratio (SNR). We propose a PC transmitter allowing fast and precise code generation with small power consumption and chip area, and also offering reconfigurable capability. Compared with previously reported UWB pulse radars with relatively simple coding schemes, the proposed transmitter features a much more challenging 15-bit pseudonoise code design using high-speed shift registers, which can improve SNR up to 23.5 dB. The measured results demonstrate correct output waveforms corresponding to different modulation codes with the spectrum well confined under the regulation mask. With a modulation rate over 3 Gb/s (pulse repeat frequency of 6.125 MHz), a resolution of 5 cm can be achieved. Index Terms-Automotive radar, CMOS, K-band, pulse compression (PC), transmitter, ultra-wideband (UWB). University. His current research interests include the design of monolithicmicrowave integrated circuits (MMICs) and RF integrated circuits (RFICs) using Si/III-V-based technologies. He is involved with the design, fabrication, and the modeling of high-frequency transistors and interconnects. He is also interested in heterogeneous integration using system-in-package (SiP) and 3-D integrated circuit (IC) technology for high-speed wireless/optical communications.

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“…This removes the need for differential clock generation as in CML, and skew/overlapping issues [5]. Recently, different TSPC-based topologies have been proposed to include the logic gates that select the divider mode within the Flip-Flops (FFs) in order to reduce the number of stages in cascade.…”

Section: Compact and High-speed Frequency Prescalermentioning

confidence: 99%

A 36GHz/mw single-phase prescaler using implication logic in 0.13μm CMOS

Roa

Chen

Jung

2013

2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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This paper presents a non-Boolean digital logic technique used in the design of a high-speed and low-power frequency prescaler. Maximum achievable frequency input of prescalers is limited by the number of devices connected in cascade to the high-speed signal path. In this work, a reduced number of devices is obtained in the prescaler by realizing implication logic operators with a single-phase digital-based flip-flop. The prescaler is implemented in 0.13µm CMOS with a 1.2V supply. A measured efficiency of 36GHz per mW is achieved which represents 3X power consumption reduction compared to prior art in the same technology node, and the highest efficiency reported.

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A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHz

Cited by 21 publications

References 3 publications

Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology

Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology

A K-Band Reconfigurable Pulse-Compression Automotive Radar Transmitter in 90-nm CMOS

A 36GHz/mw single-phase prescaler using implication logic in 0.13μm CMOS

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A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHz

Cited by 21 publications

References 3 publications

Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology

Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology

A K-Band Reconfigurable Pulse-Compression Automotive Radar Transmitter in 90-nm CMOS

A 36GHz/mw single-phase prescaler using implication logic in 0.13&#x03BC;m CMOS

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A 36GHz/mw single-phase prescaler using implication logic in 0.13μm CMOS