The design, fabrication, and characterization of a novel low-frequency meandering piezoelectric vibration energy harvester is presented. The energy harvester is designed for sensor node applications where the node targets a width-to-length aspect ratio close to 1:1 while simultaneously achieving a low resonant frequency. The measured power output and normalized power density are 118 μW and 5.02 μW/mm(3)/g(2), respectively, when excited by an acceleration magnitude of 0.2 g at 49.7 Hz. The energy harvester consists of a laser-machined meandering PZT bimorph. Two methods, strain-matched electrode (SME) and strain-matched polarization (SMP), are utilized to mitigate the voltage cancellation caused by having both positive and negative strains in the piezoelectric layer during operation at the meander's first resonant frequency. We have performed finite element analysis and experimentally demonstrated a prototype harvester with a footprint of 27 x 23 mm and a height of 6.5 mm including the tip mass. The device achieves a low resonant frequency while maintaining a form factor suitable for sensor node applications. The meandering design enables energy harvesters to harvest energy from vibration sources with frequencies less than 100 Hz within a compact footprint.

Abstract-A 43-GHz wireless inter-chip data link including antennas, transmitters, and receivers is presented. The industry standard bonding wires are exploited to provide high efficiency and low-cost antennas. This type of antennas can provide an efficient horizontal communication which is hard to achieve using conventional on-chip antennas. The system uses binary amplitude shift keying (ASK) modulation to keep the design compact and power efficient. The transmitter includes a differential to single-ended modulator and a two-stage power amplifier (PA). The receiver includes a low-noise amplifier (LNA), pre-amplifiers, envelope detectors (ED), a variable gain amplifier (VGA), and a comparator. The chip is fabricated in 180-nm SiGe BiCMOS technology. With power-efficient transceivers and low-cost high-performance antennas, the implemented inter-chip link achieves bit-error rate (BER) around 10 8 for 6 Gb/s over a distance of 2 cm. The signal-to-noise ratio (SNR) of the recovered signal is about 24 dB with 18 ps of rms jitter. The transmitter and receiver consume 57 mW and 60 mW, respectively, including buffers. The bit energy efficiency excluding test buffers is 17 pJ/bit. The presented work shows the feasibility of a low power high data rate wireless inter-chip data link and wireless heterogeneous multi-chip networks.Index Terms-Bond-wire antenna, high-speed link, on-chip antenna, wirebond antenna, wireless inter-chip link, wireless transceiver.

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Abstract-Energy conservation is essential in wireless sensor networks (WSNs) because of limited energy in nodes' batteries. Collaborative beamforming uses multiple transmitters to form antenna arrays; the electromagnetic waves from these antenna arrays can create constructive interferences at the receiver and increase the transmission distance. Each transmitter can use lower power and save energy, since the energy consumption is spread over multiple transmitters. However, if the same nodes are always used, these nodes would deplete their energy much sooner and this sensing area will no longer be monitored. To avoid this situation, energy consumption for collaborative beamforming needs to be balanced over the whole network by assigning the transmitters in turns. The transmitters in each round are selected by a scheduler and the energy carried in each node is balanced to increase the number of transmissions. The lifetime of a network is the number of transmissions until a certain percentage of the nodes depletes their energy. This paper proposes an algorithm to calculate energy-efficient schedules based on the remaining energy and the phase differences of their signals arriving at the receiver. Compared with an existing algorithm, our algorithm can extend the network lifetime by more than 60%.

Blind zone in a phase-frequency detector (PFD) reduces the input detection range and aggravates cycle slips. This brief analyzes the blind zone in latch-based PFDs and proposes a technique that removes the blind zone caused by the precharge time of the internal nodes. With the proposed technique, the PFD achieves a small blind zone close to the limit imposed by process-voltage-temperature variations. The comparison between the proposed design and previous works is presented. Fabricated in a 130-nm CMOS technology, the measured blind zone is 61 ps, which is smaller than that of the existing topologies by almost 100 ps.

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