A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves

Decanis, Ugo; Ghilioni, Andrea; Monaco, Enrico; Mazzanti, Andrea; Svelto, F.

doi:10.1109/jssc.2011.2162468

Cited by 72 publications

(34 citation statements)

References 22 publications

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“…Fundamental voltage controlled oscillators (VCOs) at frequencies above 50 GHz [4]- [12] typically suffer from relatively poor phase noise even while dissipating significant power. Moreover, it becomes extremely challenging to obtain sufficient tuning range for target applications at these frequencies.…”

Section: Introductionmentioning

confidence: 99%

A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance

Sadhu

Ferriss

Valdes‐Garcia

2015

IEEE J. Solid-State Circuits

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This paper introduces a 2nd harmonic extraction technique and its implementation in a 46.4-58.1 GHz frequency synthesizer. The frequency doubling approach is based on tapping second harmonic signals at the VCO supply and tail nodes and amplifying them to provide a differential output. Since the amplifiers do not load the VCO outputs, the proposed technique does not affect either the tuning range or the frequency of the VCO. Moreover, a novel noise bypass technique is utilized to ensure that the amplifiers do not degrade the VCO phase noise. As a result, the frequency synthesizer achieves 22.4% tuning range (46.4-58.1 GHz) and phase noise below -118 dBc/Hz while consuming 66 mW from a 1 V supply. The stacked common gate amplifier can also be utilized for voltage regulation, providing a relatively constant FOM performance over a 2X power dissipation range. The synthesizer occupies 0.6 mm 1 mm in IBM 32 nm SOI CMOS.

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Section: Introductionmentioning

confidence: 99%

A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance

Sadhu

Ferriss

Valdes‐Garcia

2015

IEEE J. Solid-State Circuits

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“…However, it is apparent that when the flux linkage is maximum (i.e., k = 1), the effective inductance can be reduced to zero but cannot be negative. This reduction in flux linkage is a drawback of the use of solid ground shields to isolate planar inductors from solid state substrates [13], and has been used to intentionally reduce the coupling in planar transformers [14]. Note that by putting a switch in the secondary, the inductance can be toggled between two values.…”

Section: Device Conceptmentioning

confidence: 99%

“…Note that by putting a switch in the secondary, the inductance can be toggled between two values. This principle has been used by several research groups to realize switch-reconfigurable inductors [13][14][15][16][17][18][19]. Tunable inductors have also been reported that are based on changing the bias on a magnetic material in the flux path [20,21].…”

Section: Device Conceptmentioning

confidence: 99%

Active Negative Inductor Based on Magnetic Flux

Stancil¹

2012

PIER C

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Abstract-An active circuit is described that exhibits the equivalent reactance of a negative inductor. In contrast with previous techniques based on negative impedance converters, the negative inductance is produced by generating an opposing time-varying magnetic flux. The new circuit also enables the inductance to be electronically varied between negative and positive values, can enhance the Q, and defaults to a conventional positive inductor in the event of active component failure. The performance of a prototype with an inductance of −0.344 mH and operating over the frequency range 1-40 kHz is described.

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“…2a, reduces to a clocked differential pair working as a dynamic CML latch. We have recently proved that, for the same power dissipation, this solution leads to a 2x improvement in speed and allows the design of compact mm-wave dividers at limited power dissipation [7,8]. This paper presents further investigations on dynamic CML latches aimed at realizing high performance mm-wave dividers.…”

Section: Introductionmentioning

confidence: 99%

“…Dynamic CML latch as presented in[7,8] (a), and modified CML latch clocked on both the tail current source and pMOS loads (b).…”

mentioning

confidence: 99%

A 4.8mW inductorless CMOS frequency divider-by-4 with more than 60% fractional bandwidth up to 70GHz

Ghilioni

Decanis

Mazzanti

et al. 2012

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference

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Frequency synthesizers at mm-waves would benefit from wide-band low-power dividers with large division factors. This work proposes a divider-by-4 based on clocked differential amplifiers working as dynamic CML latches. The clock modulates both the tail current and the load resistance of the differential pair, allowing a wide locking range. Prototypes, realized in 32nm CMOS, operate between 14GHz and 70GHz demonstrating a fractional bandwidth in excess of 60% in the entire range, 4.8mW of maximum power consumption and 55x18µm 2 occupied area.Index Terms-Millimeter wave circuits, Wideband, Low power electronics, Frequency divider and CMOS technology.

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A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves

Cited by 72 publications

References 22 publications

A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance

A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance

Active Negative Inductor Based on Magnetic Flux

A 4.8mW inductorless CMOS frequency divider-by-4 with more than 60% fractional bandwidth up to 70GHz

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