A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS

Today’s computing challenges: opportunities for computer hardware design

“…However, the interconnect partially takes advantage of the technology scaling, because faster transistors enable a better circuit to overcome the increased channel loss. Figure 11A shows a survey from the state-of-the-art published works ( Tamura et al, 2001 ; Haycock & Mooney, 2001 ; Tanaka et al, 2002 ; Lee et al, 2003 , 2004 ; Krishna et al, 2005 ; Landman et al, 2005 ; Casper et al, 2006 ; Palermo, Emami-Neyestanak & Horowitz, 2008 ; Kim et al, 2008 ; Lee, Chen & Wang, 2008 ; Amamiya et al, 2009 ; Chen et al, 2011 ; Takemoto et al, 2012 ; Raghavan et al, 2013 ; Navid et al, 2014 ; Zhang et al, 2015 ; Upadhyaya et al, 2015 ; Norimatsu et al, 2016 ; Gopalakrishnan et al, 2016 ; Shibasaki et al, 2016 ; Peng et al, 2017 ; Han et al, 2017 ; Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ), where we can confirm the correlation between the technology node and the data rate. On the other hand, however, overcoming the increased channel loss has become more and more expensive as the loss is going worse as the bandwidth increases; the equalization circuits consume too much power to compensate the loss, which makes people hesitant to increase the bandwidth.…”

“…Recently, a dramatic change has been made to break the ice. An amplitude modulation technique, which is called 4-level pulse-amplitude modulation (PAM-4), has been adopted in the industry ( Upadhyaya et al, 2018 ; Wang et al, 2018 ; Depaoli et al, 2018 ; Tang et al, 2018 ; LaCroix et al, 2019 ; Pisati et al, 2019 ; Ali et al, 2019 , 2020 ; Im et al, 2020 ; Yoo et al, 2020 ). With PAM-4, the interconnect can transmit two bits in one-bit period, which doubles the effective bandwidth over NRZ.…”

Hysteretic Error Extraction in Multi-Level Wireline Receivers

“…Furthermore, there is a bandwidth penalty due to the impact of the input capacitors of the slicers. The increased input capacitance loads the input pads in mixedsignal DFE realizations [4], decreasing the frontend bandwidth. Moreover, the fanout of the clock distribution network driving the data and error slicers should be optimized to achieve minimum power consumption.…”

A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS

“…As the demand of bandwidth increases, multi-PAM signaling such as PAM-4 has emerged as a solution for the next generation of high-speed wireline transceivers owing to the lower Nyquist frequency and higher power efficiency [1][2][3][4]. Nevertheless, the sampling phase is more critical for PAM-4 signaling as the eye width and eye height is much smaller compared to NRZ due to the fourlevel modulation [2].…”

“…1 (c, d), degrading the BER as a whole [5,6]. One solution is to use an additional clock CLKMONITOR to measure the eye height in different sampling phase [3]. However, it increases the power consumption as it needs additional phase rotators and high speed slicers.…”