2021 IEEE International Symposium on Circuits and Systems (ISCAS) 2021
DOI: 10.1109/iscas51556.2021.9401568
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Hysteretic Error Extraction in Multi-Level Wireline Receivers

Abstract: A wireline receiver complexity reduction approach achieved by using hysteretic extraction of the error for phase detection is presented in this paper. The approach is based on the utilization of the data slicers intended for speculative level detection to perform a hysteretic estimation of the error signal. Simulation results showed better jitter tolerance and better eye margin for the proposed hysteretic receiver compared to prior approaches for low loss channels, while reducing the complexity by 64%.

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