A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS

Abstract

A 25Gb/s PAM-4 receiver is presented with 4tap adaptive DFE and sampling clock optimization. PAM-4 signaling suffers more from non-optimal sampling clock phase which degrades BER. By finding the point with the least pre-cursor ISI, the sampling clock can be recovered with optimal phase, which improves the BER by as much as 10 9 through 12.5dB channel loss. A novel clocked amplifier is implemented as a slicer to reduce the loop delay and meet the timing constraints of the direct feedback. Fabricated in 55nm CMOS technology, the receiver occupies 0.27mm 2 and consumes 185mW at 25Gb/s with a power supply of 1.2V.