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Ferroelectric random access memory (FeRAM) is an attractive candidate technology for embedded nonvolatile memory, especially in applications where low power and high program speed are important. Market introduction of high-density FeRAM is, however, lagging behind standard complementary metal-oxide semiconductor (CMOS) because of the difficult integration technology. This paper discusses the major integration issues for high-density FeRAM, based on SrBi2Ta2O9 (strontium bismuth tantalate or SBT), in relation to the fabrication of our stacked cell structure. We have worked in the previous years on the development of SBT-FeRAM integration technology, based on a so-called pseudo-three-dimensional (3D) cell, with a capacitor that can be scaled from quasi two-dimensional towards a true three-dimensional capacitor where the sidewalls will importantly contribute to the signal. In the first phase of our integration development, we integrated our FeRAM cell in a 0.35μm CMOS technology. In a second phase, then, possibility of scaling of our cell is demonstrated in 0.18μm technology. The excellent electrical and reliability properties of the small integrated ferroelectric capacitors prove the feasibility of the technology, while the verification of the potential 3D effect confirms the basic scaling potential of our concept beyond that of the single-mask capacitor. The paper outlines the different material and technological challenges, and working solutions are demonstrated. While some issues are specific to our own cell, many are applicable to different stacked FeRAM cell concepts, or will become more general concerns when more developments are moving into 3D structures.

The difficult scaling of ferroelectric random access memories with the complementary metal-oxide semiconductor technology roadmap requires integration of three-dimensional (3D) ferroelectric capacitors (FeCAP’s). In this work the unusual electrical behavior of 3D FeCAP sidewalls was studied by comparing the electrical properties of two-dimensional and 3D integrated FeCAP structures. We evidenced composition variations of the SrBi2Ta2O9 (SBT) film in the sidewalls with marked bismuth segregation during metal-organic chemical-vapor deposition (MOCVD) of the SBT film. The segregation was reduced after decreasing the deposition temperature from 440°C, whereby the Bi-rich phase in the sidewalls does not contribute to polarization, down to 405°C, whereby sidewall SBT contributes to polarization. After further optimization of the MOCVD conditions at 405°C, the segregation is minimized and the ferroelectric contribution of the sidewall SBT is almost the same as the contribution of the planar SBT. As a result, 3D FeCAP’s integrated up to metal interconnection exhibit a remnant polarization Pr∼7.5μC∕cm2.

In many applications up to millions of sensors or actuators have to be interconnected to each other and/or to the outside world, making the monolithic integration of circuitry mandatory. This monolithic integration is also pursued for mass-produced transducers because of economical reasons. CMOS-integrated transducers are thus found in imaging transducers arrays and mass-produced physical sensors. In addition, integrated biochemical sensor arrays can be CMOS-integrated.In this article ®rst a general overview of the ®eld is given and then selected work in the imaging and biochemical ®eld is highlighted. Concerning imaging transducer arrays an overview is given of visible and IR imagers, displays and of inkjet printheads. Concerning the new ®eld of biochemical sensor arrays, two examples are described: a blood-gas sensor and an array of interdigitated electrodes. Finally an overview of the possible technological approaches regarding integrated processing of transducers is presented.

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The thermal and mechanical stability of Ir and Ir\Pt metals spacers deposited on top of Ti(Al)N\Ir\IrO 2 patterned structures has been investigated in pseudo 3D stacked SrBi 2 Ta 2 O 9 (SBT) capacitors. Their stability was compared to standard TEOS spacers. The high compressive stress at the edge of patterned electrodes, as a consequence of the high thermal expansion mismatch between the metals used in the electrode and TEOS, make the system mechanically unstable at the SBT crystallization conditions (700 • C for 1 hour). The mechanical problems could be overcome if the same noble metals used in the electrode are incorporated as spacers. However, thermal stability during the SBT crystallization conditions is still an issue. For the case of Ir, surface oxidation decreases the SBT polarization values. In the case of Ir\Pt, Ir diffuses through Pt and oxidizes, leading to unstable patterned structures and to the oxidation of the Ti(Al)N layer.

In our integration scheme, a “pseudo-3D” capacitor cell is used where the TiAlN\Ir\IrO2\Pt bottom electrode is patterned before SBT deposition. In order to understand how this system behaves mechanically, we have investigated the evolution of the stress of blanket Sr1-xBi2+yTa2O9 (x, y < 0.5) layers deposited on this pre-patterned bottom electrode stack. SBT was deposited by metal organic vapor deposition (MOCVD) between 405 °C and 440 °C. The stresses were monitored by the change in the radius of curvature of the wafer at the subsequent processing steps: deposition of electrodes and SBT, crystallization and recovering annealing, and after removal of Pt top electrode, SBT and bottom electrode layers by dry etching. The stress conditions observed for the different planar layers as a function of the SBT deposition temperature was correlated to the TiAlN lateral oxidation length observed in the etched structure after the SBT crystallization step.