Stress evolution in integrated SrBi₂Ta₂O₉ ferroelectric layers

Abstract

In our integration scheme, a “pseudo-3D” capacitor cell is used where the TiAlN\Ir\IrO2\Pt bottom electrode is patterned before SBT deposition. In order to understand how this system behaves mechanically, we have investigated the evolution of the stress of blanket Sr1-xBi2+yTa2O9 (x, y < 0.5) layers deposited on this pre-patterned bottom electrode stack. SBT was deposited by metal organic vapor deposition (MOCVD) between 405 °C and 440 °C. The stresses were monitored by the change in the radius of curvature of the wafer at the subsequent processing steps: deposition of electrodes and SBT, crystallization and recovering annealing, and after removal of Pt top electrode, SBT and bottom electrode layers by dry etching. The stress conditions observed for the different planar layers as a function of the SBT deposition temperature was correlated to the TiAlN lateral oxidation length observed in the etched structure after the SBT crystallization step.

Integration of ferroelectric SrBi2Ta2O9-based capacitors in 0.35μm CMOS technology

“…4). The microstructural characteristics of each layer and the thermo-mechanical stability investigations of the integrated BE\SBT\Pt FeCAP's structure have been published elsewhere [5,6]. As a brief summary, we have observed that Ir and Pt layers mainly define the overall stress of the stack [3].…”

“…The characteristic tensile stress of the SBT MOCVD layer increases as the deposition temperature increases, opening up the TiAlN-Ir interface and producing a longer oxygen diffusion path. For example, for SBT films deposited at 405 °C (stress ~ +0.8 GPa) and 440 °C (stress ~ +1.0 GPa) the TiAlN lateral oxidation varies from 200 nm to 230 nm, respectively, for the same annealing conditions [6]. Further work using finite elements simulations is on going for having a better understanding of the thermo-mechanical behavior of our cell capacitors, a key factor for successful integration.…”