Integration of ferroelectric SrBi2Ta2O9-based capacitors in 0.35μm CMOS technology

Lisoni, J. G.; Johnson, J. A.; Goux, L.; Schwitters, M.; Paraschiv, Vasile; Maes, David; Haspeslagh, L.; Caputa, C.; Casella, P.; Zambrano, R.; Vecchio, Giovanna Del; Monchoix, H.; Autryve, L. Van; Wouters, Dirk J.

doi:10.1002/pssc.200404886

Cited by 5 publications

(2 citation statements)

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“…The Pt bottom electrode was sputtered on an IrO 2 /Ir/Ti͑Al͒N/Si stack originally used for oxygen barrier properties. 11 Amorphous Sr-Ta-O ͑ST͒ and Bi-Ta-O ͑BT͒ films were deposited at 360°C in a mixture of Ar and O 2 by MOCVD, using the liquid precursors Bi͑thd͒ 3 , Sr͑thd͒ 2 pmdeta, and Ta͑O-iPr͒ 4 ͑thd͒. The use of separate precursors gave flexibility to tailor the composition of the films.…”

Section: Methodsmentioning

confidence: 99%

Metallorganic Chemical Vapor Deposition of Sr-Ta-O and Bi-Ta-O Films for Backend Integration of High-k Capacitors

Goux

Meeren

Wouters

2006

J. Electrochem. Soc.

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Dielectric layers with high dielectric constant, low leakage, and high breakdown strength are of great interest for application in devices such as Dynamic random access memory, decoupling capacitors, or impedance matching capacitors. However, some applications require complementary metal oxide semiconductor backend integration of those capacitors, with low-temperature processing. In this work, we prepare Pt/Sr-Ta-O/Pt and Pt/Bi-Ta-O/Pt capacitors on silicon, where dielectrics are deposited at 360°C by metallorganic chemical vapor deposition ͑MOCVD͒. After capacitor fabrication, a minimal leakage is obtained for a recovery anneal at a temperature of 500°C for Pt/Sr-Ta-O/Pt and 300°C for Pt/Bi-Ta-O/Pt. We show that both types of dielectrics are promising for incorporation in backend integrated high-k capacitors. Particularly, their leakage level is lower than reported for other dielectrics, which constitutes a significant advantage for memory application. The results also suggest that MOCVD is a suited technique to obtain very thin Sr-Ta-O and Bi-Ta-O films which are dense, smooth, and with good interfacial quality.Dielectric layers with high dielectric constant, low leakage, and high breakdown strength are of great importance and have a wide range of applications in semiconductor devices. High-k dielectrics are being extensively developed for gate dielectric replacement in complementary metal oxide semiconductor ͑CMOS͒ technology, as well as for application in dynamic random access memory ͑DRAM͒. In the latter case, capacitance densities of 10 F/cm 2 together with low leakage ͑Ͻ10 −9 A/cm 2 ͒ are attainable using thin crystalline films prepared by metallorganic chemical vapor deposition ͑MOCVD͒. 1 However, that approach requires process temperatures exceeding 500°C, which is not suitable for integrated passive applications. The need for high capacitances integrated in the wiring level of circuitry is increasing. For example, decoupling capacitances are needed on logic integrated circuits for high-frequency operation to decrease the inductance between the source of charge and the clocking transistor, while application-specific integrated circuits ͑ASIC's͒ used in radio-frequency applications require high capacitances with low loss for impedance matching. 2 Some ASIC's also need memories having high capacitance and low leakage integrated in the upper wiring layers. For those applications, process temperatures should be lower than 400°C if Cu/low k interconnects are used.Several materials such as Al 2 O 3 , 3,4 Ta 2 O 5 , 5-7 ZrO 2 , 8 Y 2 O 3 , 9 or HfO 2 ͑Ref. 10͒ have been recently studied for these applications. In the present work, we investigate the electrical properties of metalinsulator-metal ͑MIM͒ capacitors using Sr-Ta-O and Bi-Ta-O dielectrics that are deposited by MOCVD as amorphous layers on Pt substrates at 360°C. We discuss their advantages over other materials and their potential applications. ExperimentalThe capacitors were realized as follows. The Pt bottom electrode was sputtered on an IrO 2 /Ir/Ti...

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Section: Methodsmentioning

confidence: 99%

Metallorganic Chemical Vapor Deposition of Sr-Ta-O and Bi-Ta-O Films for Backend Integration of High-k Capacitors

Goux

Meeren

Wouters

2006

J. Electrochem. Soc.

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“…The two-dimensional and three-dimensional SBT-based capacitors analysed in this paper were obtained in the following manner: after a front-end CMOS processing, a bottom electrode (denoted BE) stack, Pt/IrO 2 /Ir/Ti(Al)N, was deposited on top of a W plug and patterned in arrays of stripes (Lisoni et al, 2004). Then, an Sr 0.8 Bi 2.2 Ta 2 O 9 (SBT) film ($120 nm thick) was deposited by MOCVD at 678 K and crystallized at 973 K during 60 min in oxygen (Johnson et al, 2003).…”

Section: Preparation and Description Of The Samplesmentioning

confidence: 99%

Microstructural analysis of integrated pin-shaped two-dimensional and three-dimensional ferroelectric capacitors from micro-focused synchrotron X-ray techniques

et al. 2006

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Future development of ferroelectric random access memory requires the integration of three-dimensional ferroelectric capacitors (FeCAP) in a microelectronic architecture. In this paper, pin-shaped two-dimensional and three-dimensional Sr 0.8 Bi 2.2 Ta 2 O 9 -based FeCAP arrays were characterized using an original approach combining micro-focused synchrotron X-ray fluorescence and diffraction. From a modelling approach, dimensional, chemical and microstructural details were extracted over a series of capacitor arrays. Hence, these techniques proved insightful for a non-destructive benchmarking approach. In addition, for all investigated capacitor geometries, the microfluorescence experiments evidenced a well controlled chemical composition within the FeCAP arrays, attesting the stability of the elaboration and integration steps. Nevertheless, micro-diffraction experiments have indicated a lower control of the ferroelectric film crystallographic orientation from one capacitor to the next, despite a well defined chemical composition. This feature was attributed to the presence of patterned bottom electrodes, bringing to light the role of the slanted capacitor sidewalls in the three-dimensional geometry and partially explaining the non-optimized electrical polarization usually measured in three-dimensional capacitors with respect to planar geometry. research papers J. Appl. Cryst. (2006). 39, 376-384 N. Menou et al. Integrated pin-shaped ferroelectric capacitors 377

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Sidewalls contribution in integrated three-dimensional Sr0.8Bi2.2Ta2O9-based ferroelectric capacitors

Menou

Turquat

Madigou

et al. 2005

Applied Physics Letters

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As compared to usual planar capacitors, three-dimensional (3D) ferroelectric capacitors display a large polarization increase due to the additional electrical contribution of the capacitor sidewalls. However, in 3D capacitors the polarization increase with respect to the planar geometry is lower than expected. To uncover the origin of this discrepancy, the microstructure of 3D Sr0.8Bi2.2Ta2O9-based (SBT) capacitors was studied. First, high-resolution synchrotron x-ray diffraction has found a unit cell expansion of the SBT phase in the capacitor sidewalls. From local chemical analyses, this lattice distortion has been correlated to composition variations in this region. These microstructural changes are due to the peculiar topography of the etched bottom electrode and to the variety of layers in contact with the SBT film, which can explain the nonoptimized polarization in 3D capacitors.

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Integration of ferroelectric SrBi2Ta2O9-based capacitors in 0.35μm CMOS technology

Cited by 5 publications

References 11 publications

Metallorganic Chemical Vapor Deposition of Sr-Ta-O and Bi-Ta-O Films for Backend Integration of High-k Capacitors

Metallorganic Chemical Vapor Deposition of Sr-Ta-O and Bi-Ta-O Films for Backend Integration of High-k Capacitors

Microstructural analysis of integrated pin-shaped two-dimensional and three-dimensional ferroelectric capacitors from micro-focused synchrotron X-ray techniques

Sidewalls contribution in integrated three-dimensional Sr0.8Bi2.2Ta2O9-based ferroelectric capacitors

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