Why CMOS-integrated transducers? A review

Witvrouw, Ann; Steenkiste, F. Van; Maes, David; Haspeslagh, L.; Gerwen, P. Van; Moor, Piet De; Sedky, Sherif; Hoof, Chris Van; Vries, Annemarie C. de; Verbist, Agnes; Caussemaeker, A. De; Parmentier, Brigitte; Baert, Kris

doi:10.1007/s005420000050

Cited by 28 publications

(12 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Firstly, to reduce the system size, we adopted an above-IC MEMS process in which MEMS is formed just above the CMOS layer [5,6]. As a package, a WLCSP is used to minimize the system volume.…”

Section: Introductionmentioning

confidence: 99%

A CMOS embedded RF-MEMS tunable capacitor for multi-band/multi-mode smartphones

Kurui

Yamazaki

Shimooka

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

View full text Add to dashboard Cite

This paper reports on 1-chip RF-MEMS tunable capacitor that equips CMOS driver circuit in the underlying layer. A Wafer Level Chip Scale Package (WLCSP) optimized for RF-MEMS is employed to minimize the module size.The MEMS actuation voltage is generated by an Actuation Voltage Generator (AVG). The boost mechanism employed in the AVG enables instant high voltage generation and reduction of the dielectric charging. The measured noise at RF frequencies is less than -120dbm, thanks to a shield metal layer formed between MEMS and CMOS layers.To achieve high power handing and high creep immunity, we employ the previously reported techniques, the Quadruple Series Capacitor (QSC) [1] and the SiN springs [2]. The quality factor measured in the WLCSP is larger than 100 at 1GHz. The capacitance can be changed from 1.4pF to 5pF by a step of 0.45pF.

show abstract

Section: Introductionmentioning

confidence: 99%

A CMOS embedded RF-MEMS tunable capacitor for multi-band/multi-mode smartphones

Kurui

Yamazaki

Shimooka

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

View full text Add to dashboard Cite

show abstract

“…The CMOS technology has allowed the batch fabrication of microdevices integrated with signal readout circuits [ 4 – 9 ], which is called monolithic CMOS-MEMS technology [ 10 , 11 ]. The microstructures designed on a CMOS chip can be released using a post-processing of the chip [ 12 – 16 ], which generally includes some surface or bulk micromachining process.…”

Section: Introductionmentioning

confidence: 99%

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

López-Huerta

Herrera-May

Estrada-López

et al. 2011

Sensors

View full text Add to dashboard Cite

We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

show abstract

“…Procedures such as exposure to the UVlight is thus necessary to remove the residual charges before usage [15]. Therefore, variants such as the discrete-gate structure coated with a sensitive membrane [19,20], or the field-effect transistors with gate omitted [21,22] [22] is created by plasma etching, which could damage the field-effect transistor easily or introduce extra mismatches, as will be discussed in this paper. This paper proposes two post-CMOS processes for fabricating open-gate, field-effect transistors (OGFETs) at the die level.…”

Section: Introductionmentioning

confidence: 99%

Die-level, post-CMOS processes for fabricating open-gate, field-effect biosensor arrays with on-chip circuitry

Chang¹,

Chang²,

Lin³

et al. 2008

J. Micromech. Microeng.

View full text Add to dashboard Cite

Field-effect sensors have been applied extensively to numerous biomedical applications. To develop biosensor arrays in large scale, integration with signal-processing circuits on a single chip is crucial for avoiding wiring complexity and reducing noise interference. This paper proposes and compares two CMOS-compatible processes that allow open-gate, field-effect transistors (OGFETs) to be fabricated at the die level. The polygates of transistors are removed to maximize the transconductance. The CMOS compatibility further facilitates the monolithic integration with circuitry. Based on images and electrical measurements taken at different stages of the post-CMOS processes, a more feasible and reliable process is identified. The robustness of the fabricated OGFETs against the micromachining process and against moisture is further examined and discussed. Finally, the capability of the OGFETs in detecting ion concentrations, biomolecules, and electrophysiological signals is demonstrated.

show abstract

Why CMOS-integrated transducers? A review

Cited by 28 publications

References 6 publications

A CMOS embedded RF-MEMS tunable capacitor for multi-band/multi-mode smartphones

A CMOS embedded RF-MEMS tunable capacitor for multi-band/multi-mode smartphones

Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

Die-level, post-CMOS processes for fabricating open-gate, field-effect biosensor arrays with on-chip circuitry

Contact Info

Product

Resources

About