Die-level, post-CMOS processes for fabricating open-gate, field-effect biosensor arrays with on-chip circuitry

Abstract

Field-effect sensors have been applied extensively to numerous biomedical applications. To develop biosensor arrays in large scale, integration with signal-processing circuits on a single chip is crucial for avoiding wiring complexity and reducing noise interference. This paper proposes and compares two CMOS-compatible processes that allow open-gate, field-effect transistors (OGFETs) to be fabricated at the die level. The polygates of transistors are removed to maximize the transconductance. The CMOS compatibility further facilitates the monolithic integration with circuitry. Based on images and electrical measurements taken at different stages of the post-CMOS processes, a more feasible and reliable process is identified. The robustness of the fabricated OGFETs against the micromachining process and against moisture is further examined and discussed. Finally, the capability of the OGFETs in detecting ion concentrations, biomolecules, and electrophysiological signals is demonstrated.

Exploiting CMOS Technology to Enhance the Performance of ISFET Sensors

“…Additional parasitic effects include the relatively low transconductance of ISFETs in unmodified CMOS [9], [10] (compared to MOSFETs counterparts), due to the higher overall thickness of insulating layers deposited on the ISFET's channel. This letter presents a novel ISFET structure that has been developed in unmodified CMOS, without requiring postprocessing steps as in [11]. The remote gate of the device comprises of a polysilicon/aluminum extended gate with the overlying intermetal dielectric (IMD) being utilized as the sensing membrane (Fig.…”

FET-based biosensor incorporating a conductometric bioreceptor

“…The conductometric element can be deposited on the oxide field by techniques compatible with microelectronic industry, such as spin coating. Beyond of this, as occurs in the case o the extended gate ISFETs, the sampling area of the proposed device becomes independent of the gate area of the transistor which is small for current devices in production lines [6][7][8].…”

A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors

“…), including systems-on-chip. Examples range from MEMS (microelectromechanical) integrated systems [ 1 , 2 ] to microfluidic devices [ 3 , 4 , 5 , 6 ], and bio/chemical sensors [ 7 , 8 , 9 , 10 , 11 ]. Among those applications, the development of wireless microscale neural implants using CMOS has been explored as one approach for next-generation brain–machine interfaces (BMI) by several groups [ 12 , 13 , 14 , 15 , 16 , 17 , 18 ].…”