A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors

Abstract

Implantable active electronic microchips are being developed as multinode in-body sensors and actuators. There is a need to develop high throughput microfabrication techniques applicable to complementary metal–oxide–semiconductor (CMOS)-based silicon electronics in order to process bare dies from a foundry to physiologically compatible implant ensembles. Post-processing of a miniature CMOS chip by usual methods is challenging as the typically sub-mm size small dies are hard to handle and not readily compatible with the standard microfabrication, e.g., photolithography. Here, we present a soft material-based, low chemical and mechanical stress, scalable microchip post-CMOS processing method that enables photolithography and electron-beam deposition on hundreds of micrometers scale dies. The technique builds on the use of a polydimethylsiloxane (PDMS) carrier substrate, in which the CMOS chips were embedded and precisely aligned, thereby enabling batch post-processing without complication from additional micromachining or chip treatments. We have demonstrated our technique with 650 μm × 650 μm and 280 μm × 280 μm chips, designed for electrophysiological neural recording and microstimulation implants by monolithic integration of patterned gold and PEDOT:PSS electrodes on the chips and assessed their electrical properties. The functionality of the post-processed chips was verified in saline, and ex vivo experiments using wireless power and data link, to demonstrate the recording and stimulation performance of the microscale electrode interfaces.

Wireless Addressable Cortical Microstimulators Powered by Near-Infrared Harvesting

“…To selectively access the ONGs, each chip housed a unique ID using a 7-bit programmable fuse structure on the top metal of the chip layer (870 nm thick aluminum), available in the CMOS process. , The silicon dioxide and silicon nitride passivation layers were eliminated in the layout to expose the top metal of the fuse structure during the circuit designing process. After the CMOS fabrication, laser ablation by a nanosecond pulsed green laser (532 nm wavelength, EzLaze III laser cutting system) was performed to selectively cut the metal trace on each device to set the 7-bit addresses as follows.…”

Design and Application of MEMS-Based Hall Sensor Array for Magnetic Field Mapping

“…Apparently, a thin layer of silicon oxide was oxidized on the detection area. A PR layer was then deposited on the surface of the silicon wafer using the photolithography method [ 30 , 31 ] to pattern ( Figure 4 f) and etch the contact windows of the leads ( Figure 4 g) on each branch of the cross-shaped detection zone ( Figure 4 h). Finally, the Electron Beam Evaporation (EBE) method was used to pattern the sensor surface with Au/Cr leads for electrical connection purposes ( Figure 4 i–k).…”

Zenneck surface wave interconnect with encircle routing for effective inter chip communication

“…where R denotes the resistance, ρ is resistivity (1.724 Â 10 À6 Ω/cm), Z is trace length, X is trace width and Y is trace thickness. Expression (2) defines that the resistance of copper trace depends on the length, width and thickness parameters of the trace. The copper traces with high resistance due to decreased width will degrade the performance of e communication with respect to power dissipation and current.…”

“…Radio frequency (RF) communication between IC's featuring high compatibility towards complementary metal oxide semiconductor (CMOS) technology, less area overhead and minimal implementation cost compared to optical and 3D IC technology. 2,3 RF communication provides two implementation options like free space wireless communication and waveguide transmission. Both methods have advantages in replacing the copper traces by means of power dissipation, interference, and efficiency.…”