This paper presents an energy-efficient 12-bit successive approximation-register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary-window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spuriousfree dynamic range and signal-to-noise-and-distortion ratio. The ADC prototype occupies an active area of 0.12 mm 2 in the 0.18-μm CMOS process and consumes a total power of 0.6 mW from a 1.5-V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7-dB signal-tonoise-and-distortion ratio and 83-dB spurious-free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure-of-merit of 43 fJ/conversion-step. KEYWORDSA/D converter (ADC), binary window, D/A converter (DAC), successive approximation register (SAR)

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This study proposes a panel smooth transition regression (PSTR) model to investigate the nonlinear relationship between crude oil prices and crude oil production in 122 countries, both OPEC and non-OPEC, from March 1994 to October 2015. The statistical test for the existence of a threshold effect indicates that the relationship between oil prices and oil production is nonlinear, with different changes over time among the oil price and transition variables. Additionally, a threshold value exists. Furthermore, crude oil price volatility exhibits asymmetric responses to production volatility by fluctuating above or below the threshold value. Finally, when crude oil price volatility with a lag of two periods exceeds the threshold value, crude oil production changes have a positive impact on crude oil price volatility. In contrast, when crude oil price volatility with a lag of two periods is less than the threshold value, crude oil production changes have a negative impact on price volatility.

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AbstractThis chapter presents an energy-efficient 12-bit 1-MS/s successive approximation register analog-to-digital converter (ADC) for sensor applications. A programmable dynamic comparator is proposed to suppress static current and maintain good linearity. A hybrid charge redistribution digital-to-analog converter is proposed to decrease the total capacitance, which would reduce the power consumption of the input and reference buffers. In the proposed ADC, its total input capacitance is only 700 fF, which greatly reduces the total power consumption of the analog frontend circuits. The 12-bit ADC is fabricated using 0.18-μm complementary metal-oxidesemiconductor technology, and it consumes only 26 μW from a 1 V supply at 1-MS/s. The measured signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 60.1 and 72.6 dB, respectively. The measured effective number of bits (ENOB) for a 100 kHz input frequency is 9.7 bits. At the Nyquist input frequency, the measured SNDR and SFDR are 59.7 and 71 dB, respectively. The ENOB is maintained at 9.6 bits and the figure-of-merit is 33.5 fJ/conversion-step.